Patents by Inventor Tatsuya Kishi

Tatsuya Kishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Magnetoresistance element, magnetic memory, and magnetic head
    Publication number: 20060114716
    Abstract: There is provided a magnetoresistance element including a free layer that includes a first ferromagnetic layer and a second ferromagnetic layer whose magnetization directions are equal to each other and a nonmagnetic film intervening between the first and second ferromagnetic layers, a pinned layer including a third ferromagnetic layer that faces the free layer, and a nonmagnetic layer intervening between the free layer and the pinned layer, the nonmagnetic film containing a material selected from the group including titanium, vanadium, zirconium, niobium, molybdenum, technetium, hafnium, tungsten, rhenium, alloys thereof, semiconductors and insulators.
    Type: Application
    Filed: January 20, 2006
    Publication date: June 1, 2006
    Inventors: Tadashi Kai, Toshihiko Nagase, Tatsuya Kishi, Yoshiaki Saito
  • Magnetic memory
    Patent number: 7054187
    Abstract: A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first writing wiring extending in a first direction on or below the magnetoresistance effect element, a center of gravity of an axial cross section of the wiring being apart from a center of thickness at the center of gravity, and the center of gravity being eccentric toward the magnetoresistance effect element; and a writing circuit configured to pass a current through the first writing wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: May 30, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Kishi, Minoru Amano, Yoshiaki Saito, Shigeki Takahashi, Katsuya Nishiyama, Yoshiaki Asao, Hiroaki Yoda, Tomomasa Ueda, Yoshihisa Iwata
  • Method for producing magnetic memory device
    Patent number: 7041603
    Abstract: There is provided a magnetic memory device which has a small switching current for a writing line and which has a small variation therein. A method for producing such a magnetic memory device includes: forming a magnetoresistive effect element; forming a first insulating film so as to cover the magnetoresistive effect element; forming a coating film so as to cover the first insulating film; exposing a top face of the magnetoresistive effect element; forming an upper writing line on the magnetoresistive effect element; exposing the first insulating film on a side portion of the magnetoresistive effect element by removing a part or all of the coating film; and forming a yoke structural member so as to cover at least a side portion of the upper writing line and so as to contact the exposed first insulating film on the side portion of the magnetoresistive effect element.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: May 9, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minoru Amano, Tatsuya Kishi, Yoshiaki Saito, Tomomasa Ueda, Hiroaki Yoda
  • Magneto-resistance effect element and magnetic memory
    Patent number: 7038939
    Abstract: The magnetic memory includes a plurality of memory cells, each memory cell including: at least one writing wire; at least one data storage portion, provided on at least one portion of an outer periphery of the writing wire, which comprises a ferromagnetic material whose magnetization direction can be inverted by causing a current to flow in the writing wire; and at least one magneto-resistance effect element, disposed in the vicinity of the data storage portion, which senses the magnetization direction of the data storage portion.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: May 2, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minoru Amano, Tatsuya Kishi, Sumio Ikegawa, Yoshiaki Saito, Hiroaki Yoda
  • Magnetoresistive element and magnetic memory device
    Patent number: 7038894
    Abstract: A magnetoresistive element has a ferromagnetic double tunnel junction having a stacked structure of a first antiferromagnetic layer/a first ferromagnetic layer/a first dielectric layer/a second ferromagnetic layer/a second dielectric layer/a third ferromagnetic layer/a second antiferromagnetic layer. The second ferromagnetic layer that is a free layer consists of a Co-based alloy or a three-layered film of a Co-based alloy/a Ni—Fe alloy/a Co-based alloy. A tunnel current is flowed between the first ferromagnetic layer and the third ferromagnetic layer.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: May 2, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichiro Inomata, Kentaro Nakajima, Yoshiaki Saito, Masayuki Sagoi, Tatsuya Kishi
  • Magnetoresistive element
    Publication number: 20060082933
    Abstract: A magnetoresistive element according to an example of the present invention has a stacked structure comprised first and second ferromagnetic layers and a nonmagnetic layer disposed between these ferromagnetic layers, and a planar shape of at least one of the first and second ferromagnetic layers has a shape formed by combining two or more parts each having a shape of a character C.
    Type: Application
    Filed: October 6, 2005
    Publication date: April 20, 2006
    Inventors: Tatsuya Kishi, Masahiko Nakayama, Yoshiaki Fukuzumi, Tadashi Kai
  • Magnetoresistive element
    Publication number: 20060083057
    Abstract: A magnetoresistive element includes a first ferromagnetic layer having a first magnetization, the first magnetization having a first pattern when the magnetoresistive element is half-selected during a first data write, a second pattern when the magnetoresistive element is selected during a second data write, and a third pattern of residual magnetization, the first pattern being different from the second and third pattern, a second ferromagnetic layer having a second magnetization, and a nonmagnetic layer arranged between the first ferromagnetic layer and the second ferromagnetic layer and having a tunnel conductance changing dependent on a relative angle between the first magnetization and the second magnetization.
    Type: Application
    Filed: October 7, 2005
    Publication date: April 20, 2006
    Inventors: Masahiko Nakayama, Tadashi Kai, Tatsuya Kishi, Yoshiaki Fukuzumi, Toshihiko Nagase, Sumio Ikegawa, Hiroaki Yoda
  • Magnetic memory
    Patent number: 7023725
    Abstract: There are provided at least one wire, a magnetoresistive effect element having a storage layer whose magnetization direction varies according to a current magnetic field generated by causing a current to flow in the wire, and first yokes provided so as to be spaced from at least one pair of opposed side faces of the magnetoresistive effect element to form a magnetic circuit in cooperation with the magnetoresistive effect element when a current is caused to flow in the wire. Each of the first yokes has at least two soft magnetic layers which are stacked via a non-magnetic layer.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: April 4, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Saito, Tomomasa Ueda, Tatsuya Kishi, Minoru Amano
  • Magnetic random access memory
    Patent number: 7009873
    Abstract: A magnetic random access memory in which “0” data and “1” data are associated with resistance values of a non-magnetic layer of a magnetoresistive element, the resistance values being variable depending on orientation of magnetization of a magnetic free layer and a magnetic pinned layer which sandwich the non-magnetic layer, and current is let to flow to first and second write current paths, which are provided close to the magnetoresistive element and are separated from each other, thereby producing a composite write magnetic field, changing a direction of magnetization of the free layer, wherein the first write current path includes a channel region of an insulated-gate transistor that is disposed close to the free layer, and the transistor is controlled such that a channel current with a desired magnitude flows in the transistor.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: March 7, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Yoda, Tatsuya Kishi, Junichi Miyamoto
  • Ferromagnetic double tunnel junction element with asymmetric energy band
    Patent number: 6995962
    Abstract: There is provided a magnetoresistance effect element including a first pinned ferromagnetic layer, a second pinned ferromagnetic layer facing the first pinned ferromagnetic layer, surface regions of the first and second pinned ferromagnetic layer facing each other being different from each other in composition, a free ferromagnetic layer intervening between the first and second pinned ferromagnetic layers, a first tunnel barrier layer intervening between the first pinned ferromagnetic layer and the free ferromagnetic layer, and a second tunnel barrier layer intervening between the second pinned ferromagnetic layer and the free ferromagnetic layer.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: February 7, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Saito, Masayuki Sagoi, Minoru Amano, Kentaro Nakajima, Shigeki Takahashi, Tatsuya Kishi
  • Magnetoresistive element and magnetic memory device
    Patent number: 6987653
    Abstract: A magnetoresistive element has a ferromagnetic double tunnel junction having a stacked structure of a first antiferromagnetic layer/a first ferromagnetic layer/a first dielectric layer/a second ferromagnetic layer/a second dielectric layer/a third ferromagnetic layer/a second antiferromagnetic layer. The second ferromagnetic layer that is a free layer consists of a Co-based alloy or a three-layered film of a Co-based alloy/a Ni—Fe alloy/a Co-based alloy. A tunnel current is flowed between the first ferromagnetic layer and the third ferromagnetic layer.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: January 17, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichiro Inomata, Kentaro Nakajima, Yoshiaki Saito, Masayuki Sagoi, Tatsuya Kishi
  • Magnetic random access memory
    Patent number: 6984865
    Abstract: A magnetic random access memory concerning an example of the present invention comprises a magneto resistive element, a first insulating layer which covers side surfaces of the magneto resistive element, a second insulating layer which is arranged on the first insulating layer and has a first groove on the magneto resistive element, a write line which fills the first groove and is connected with the magneto resistive element, and a third insulating layer which is arranged between the first and second insulating layers except a bottom portion of the first groove and has an etching selection ratio with respect to at least the first and second insulating layers.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: January 10, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kajiyama, Tomomasa Ueda, Tatsuya Kishi, Hisanori Aikawa, Masatoshi Yoshikawa, Yoshiaki Asao, Hiroaki Yoda
  • Magnetoresistive element and magnetic memory
    Publication number: 20050280043
    Abstract: There are provided a first reference layer, in which a direction of magnetization is fixed, and a storage layer including a main body, in which a length in an easy magnetization axis direction is longer than a length in a hard magnetization axis direction, and a projecting portion provided to a central portion of the main body in the hard magnetization axis direction, a direction of magnetization of the storage layer being changeable in accordance with an external magnetic field.
    Type: Application
    Filed: August 30, 2005
    Publication date: December 22, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Kai, Shigeki Takahashi, Tomomasa Ueda, Tatsuya Kishi, Yoshiaki Saito
  • Magnetic random access memory and method of manufacturing the same
    Publication number: 20050281079
    Abstract: A write wiring for writing information in an MTJ device is covered with a magnetic layer. The magnetic layer has a structure in which the growing direction of columnar grains is 300 or less from the normal-line direction of sidewalls, a structure in which grains are deposited like a layer, or a structure in which grains are amorphously deposited.
    Type: Application
    Filed: August 30, 2005
    Publication date: December 22, 2005
    Inventors: Hiroaki Yoda, Hisanori Aikawa, Tomomasa Ueda, Tatsuya Kishi, Takeshi Kajiyama, Yoshiaki Asao
  • Semiconductor integrated circuit device and method of manufacturing the same
    Publication number: 20050274984
    Abstract: A semiconductor integrated circuit device includes a cell transistor; a bit line provided above the cell transistor; a magnetoresistive element provided above the bit line, a first end portion of the magnetoresistive element being electrically connected to the bit line; an intracell local interconnection provided above the magnetoresistive element, the intracell local interconnection coupling one of source and drain regions of the cell transistor to a second end portion of the magnetoresistive element; and a write word line provided above the intracell local interconnection, a portion between the write word line and the intracell local interconnection being filled with an insulator alone.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 15, 2005
    Inventors: Keiji Hosotani, Yoshiaki Asao, Yoshiaki Saito, Minoru Amano, Shigeki Takahashi, Tatsuya Kishi, Yoshihisa Iwata
  • MRAM and method of manufacturing the same
    Publication number: 20050275000
    Abstract: A magnetic memory device includes a first write wiring line including a wiring layer formed in a trench in an insulation layer, a barrier metal layer buried in the trench over the wiring layer. And the device includes a magneto-resistance effect element provided on the first write wiring line.
    Type: Application
    Filed: August 13, 2004
    Publication date: December 15, 2005
    Inventors: Takeshi Kajiyama, Hisanori Aikawa, Tomomasa Ueda, Tatsuya Kishi, Masatoshi Yoshikawa
  • Magnetic random access memory
    Publication number: 20050259464
    Abstract: A magnetic random access memory concerning an example of the present invention comprises a magneto resistive element, a first insulating layer which covers side surfaces of the magneto resistive element, a second insulating layer which is arranged on the first insulating layer and has a first groove on the magneto resistive element, a write line which fills the first groove and is connected with the magneto resistive element, and a third insulating layer which is arranged between the first and second insulating layers except a bottom portion of the first groove and has an etching selection ratio with respect to at least the first and second insulating layers.
    Type: Application
    Filed: July 27, 2005
    Publication date: November 24, 2005
    Inventors: Takeshi Kajiyama, Tomomasa Ueda, Tatsuya Kishi, Hisanori Aikawa, Masatoshi Yoshikawa, Yoshiaki Asao, Hiroaki Yoda
  • Magnetic memory device having yoke layer, and manufacturing method thereof
    Patent number: 6960815
    Abstract: A magnetic memory device includes first wiring which runs in the first direction, second wiring which runs in the second direction, a magneto-resistance element which is arranged at an intersection between the first and second wirings, a first yoke main body which covers at least either of the lower surface and two side surfaces of the first wring, a second yoke main body which covers at least either of the upper surface and two side surfaces of the second wiring, first and second yoke tips which are arranged on two sides of the magneto-resistance element in the first direction at an interval from the magneto-resistance element, and third and fourth yoke tips which are arranged on two sides of the magneto-resistance element in the second direction at an interval from the magneto-resistance element.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: November 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Yoda, Yoshiaki Asao, Tomomasa Ueda, Minoru Amano, Tatsuya Kishi, Keiji Hosotani, Junichi Miyamoto
  • Semiconductor integrated circuit device and method of manufacturing the same
    Patent number: 6958932
    Abstract: A semiconductor integrated circuit device includes a cell transistor; a bit line provided above the cell transistor; a magnetoresistive element provided above the bit line, a first end portion of the magnetoresistive element being electrically connected to the bit line; an intracell local interconnection provided above the magnetoresistive element, the intracell local interconnection coupling one of source and drain regions of the cell transistor to a second end portion of the magnetoresistive element; and a write word line provided above the intracell local interconnection, a portion between the write word line and the intracell local interconnection being filled with an insulator alone.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: October 25, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Yoshiaki Asao, Yoshiaki Saito, Minoru Amano, Shigeki Takahashi, Tatsuya Kishi, Yoshihisa Iwata
  • Magnetoresistive element and magnetic memory
    Patent number: 6949779
    Abstract: There are provided a first reference layer, in which a direction of magnetization is fixed, and a storage layer including a main body, in which a length in an easy magnetization axis direction is longer than a length in a hard magnetization axis direction, and a projecting portion provided to a central portion of the main body in the hard magnetization axis direction, a direction of magnetization of the storage layer being changeable in accordance with an external magnetic field.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: September 27, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Kai, Shigeki Takahashi, Tomomasa Ueda, Tatsuya Kishi, Yoshiaki Saito