Patents by Inventor Tatsuya Naruse

Tatsuya Naruse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128705
    Abstract: A gas laser amplifier includes a housing, discharge electrode pairs, and an optical resonator. The housing includes an entrance window that allows entry of a first laser beam from outside and an exit window that allows exit of the first laser beam amplified. Each of the discharge electrode pairs excites a laser gas supplied between discharge electrodes facing each other in the housing. The optical resonator causes a second laser beam to oscillate with a gain of the excited laser gas in a non-incident state where the first laser beam from outside the housing does not enter the housing through the entrance window. In an incident state where the first laser beam enters the housing through the entrance window, the optical resonator suspends the oscillation of the second laser beam.
    Type: Application
    Filed: November 11, 2019
    Publication date: April 18, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tatsuya YAMAMOTO, Junichi NISHIMAE, Yuzuru TADOKORO, Masashi NARUSE, Takuya KAWASHIMA
  • Publication number: 20140218831
    Abstract: An electrode pad is provided above a circuit block of a semiconductor integrated circuit device. A junction point A and a junction point B are provided on connection lines connecting electrode pads to an internal circuit and an electrostatic discharge (ESD) protection circuit. The junction point A and the junction point B are positioned at locations closer to the ESD protection circuit than to the electrode pads.
    Type: Application
    Filed: April 9, 2014
    Publication date: August 7, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Tooru MATSUI, Masanori HIROFUJI, Yoshifumi KUMASHIRO, Tatsuya NARUSE, Hiroaki SEGAWA
  • Patent number: 8773825
    Abstract: An electrode pad is provided above a circuit block of a semiconductor integrated circuit device. A junction point A and a junction point B are provided on connection lines connecting electrode pads to an internal circuit and an electrostatic discharge (ESD) protection circuit. The junction point A and the junction point B are positioned at locations closer to the ESD protection circuit than to the electrode pads.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 8, 2014
    Assignee: Panasonic Corporation
    Inventors: Tooru Matsui, Masanori Hirofuji, Yoshifumi Kumashiro, Tatsuya Naruse, Hiroaki Segawa
  • Patent number: 8669593
    Abstract: A semiconductor integrated circuit according to the present invention includes an I/O cell, a first PAD connected to the I/O cell, first and second PADs, a package wire which is connected to the first PAD and allows connection between the first PAD and an outside of the semiconductor integrated circuit, and a second package wire which is connected to the second PAD and allows connection between the second PAD and an outside of the semiconductor integrated circuit. A connection point between the first PAD and the fist package wire is located in an area where the I/O cell is placed. A connection point between the second PAD and the second package wire is located outside an area where the I/O cell is placed.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: March 11, 2014
    Assignee: Panasonic Corporation
    Inventor: Tatsuya Naruse
  • Publication number: 20120287541
    Abstract: An electrode pad is provided above a circuit block of a semiconductor integrated circuit device. A junction point A and a junction point B are provided on connection lines connecting electrode pads to an internal circuit and an electrostatic discharge (ESD) protection circuit. The junction point A and the junction point B are positioned at locations closer to the ESD protection circuit than to the electrode pads.
    Type: Application
    Filed: July 16, 2012
    Publication date: November 15, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Tooru MATSUI, Masanori HIROFUJI, Yoshifumi KUMASHIRO, Tatsuya NARUSE, Hiroaki SEGAWA
  • Publication number: 20110073915
    Abstract: A semiconductor integrated circuit according to the present invention includes an I/O cell, a first PAD connected to the I/O cell, first and second PADs, a package wire which is connected to the first PAD and allows connection between the first PAD and an outside of the semiconductor integrated circuit, and a second package wire which is connected to the second PAD and allows connection between the second PAD and an outside of the semiconductor integrated circuit. A connection point between the first PAD and the fist package wire is located in an area where the I/O cell is placed. A connection point between the second PAD and the second package wire is located outside an area where the I/O cell is placed.
    Type: Application
    Filed: December 8, 2010
    Publication date: March 31, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Tatsuya NARUSE
  • Patent number: 7514794
    Abstract: The semiconductor integrated circuit of the present invention comprises: a standard cell group including a power supply wiring group or a ground wiring group, which is arranged at an interval based upon a design rule; a connection wiring that is provided in a same layer as the standard cell group for connecting between the power supply wirings or between the ground wirings; a strap wiring that crosses with the connection wiring three-dimensionally; and a connector body for interlayer-connecting the connection wiring and the strap wiring. The connector body has a shape different from that of the power supply wiring or the ground wiring.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: April 7, 2009
    Assignee: Panasonic Corporation
    Inventors: Tatsuya Naruse, Atsushi Yamamoto
  • Publication number: 20080042284
    Abstract: The semiconductor integrated circuit of the present invention comprises: a standard cell group including a power supply wiring group or a ground wiring group, which is arranged at an interval based upon a design rule; a connection wiring that is provided in a same layer as the standard cell group for connecting between the power supply wirings or between the ground wirings; a strap wiring that crosses with the connection wiring three-dimensionally; and a connector body for interlayer-connecting the connection wiring and the strap wiring. The connector body has a shape different from that of the power supply wiring or the ground wiring.
    Type: Application
    Filed: March 16, 2007
    Publication date: February 21, 2008
    Inventors: Tatsuya Naruse, Atsushi Yamamoto
  • Patent number: 6348542
    Abstract: This invention relates to multiphase structured polymer particles comprising at least two rubber component phases (I) formed by copolymerization of monomer mixtures comprising an acrylate ester and a polyfunctional monomer, a thermoplastic resin component phase (II) formed by copolymerization of a monomer mixture comprising a methacrylate ester and other monomers, and satisfying the following conditions (1)-(5). (1) The number average molecular weight of the thermoplastic resin component forming the outermost phase is 30,000 or less. (2) The weight ratio of phase (I)/phase (II) is 30/70-80/20. (3) Of the adjacent phases (1), a specific relation holds regarding the solubility in water of the monomer mixtures forming the nth and n+1th phases. (4) A specific relation holds between the refractive index of phase (I) and the refractive index of phase (II). (5) The average particle size is 150 nm or less.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: February 19, 2002
    Assignee: Kuraray Co., Ltd.
    Inventors: Tatsuya Naruse, Takao Hoshiba, Kazutoshi Terada, Takashi Yamashita, Yuichi Katoh