Patents by Inventor Tatsuya Ohnuki

Tatsuya Ohnuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9263473
    Abstract: In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: February 16, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Ohnuki
  • Patent number: 9263451
    Abstract: A storage device in which stored data can be held even when power is not supplied, and stored data can be read at high speed without turning on a transistor included in a storage element is provided. In the storage device, a memory cell having a transistor including an oxide semiconductor layer as a channel region and a storage capacitor is electrically connected to a capacitor to form a node. The voltage of the node is boosted up in accordance with stored data by capacitive coupling through a storage capacitor and the potential is read with an amplifier circuit to distinguish data.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: February 16, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Matsubayashi, Tatsuya Ohnuki
  • Patent number: 9122896
    Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: September 1, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Ohnuki
  • Publication number: 20140332802
    Abstract: In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period.
    Type: Application
    Filed: July 23, 2014
    Publication date: November 13, 2014
    Inventor: Tatsuya Ohnuki
  • Patent number: 8847627
    Abstract: A semiconductor device includes a first transistor, a second transistor, a first transistor group, and a second transistor group. The first transistor group includes a third transistor, a fourth transistor, and four terminals. The second transistor group includes fifth to eighth transistors and four terminals. The first transistor, the third transistor, the sixth transistor, and the eighth transistor are n-channel transistors, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are p-channel transistors.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Ohnuki
  • Patent number: 8792284
    Abstract: In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: July 29, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Ohnuki
  • Publication number: 20140191791
    Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 10, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Ohnuki
  • Patent number: 8736371
    Abstract: To provide a semiconductor device with low power consumption, in a semiconductor device including a differential amplifier to which an input potential and a reference potential are input, a gain stage, and an output stage from which an output potential is output, a potential supplied from the gain stage can be held constant by providing the output stage with a transistor with low leakage current in an off state. As the transistor with low leakage current in an off state, a transistor including an oxide semiconductor layer and a channel formation region included in the oxide semiconductor layer is used.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Ohnuki
  • Patent number: 8638123
    Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: January 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Ohnuki
  • Patent number: 8520426
    Abstract: In a driving method of a semiconductor device which conducts a multilevel writing operation, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. The potential of a bit line is detected while data writing is conducted, and thereby whether a potential corresponding to the written data is normally applied to the floating gate can be confirmed without a writing verify operation.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: August 27, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Ohnuki
  • Publication number: 20120297221
    Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 22, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Tatsuya Ohnuki
  • Publication number: 20120292713
    Abstract: A semiconductor device includes a first transistor, a second transistor, a first transistor group, and a second transistor group. The first transistor group includes a third transistor, a fourth transistor, and four terminals. The second transistor group includes fifth to eighth transistors and four terminals. The first transistor, the third transistor, the sixth transistor, and the eighth transistor are n-channel transistors, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are p-channel transistors.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 22, 2012
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya OHNUKI
  • Publication number: 20120286871
    Abstract: To provide a semiconductor device with low power consumption, in a semiconductor device including a differential amplifier to which an input potential and a reference potential are input, a gain stage, and an output stage from which an output potential is output, a potential supplied from the gain stage can be held constant by providing the output stage with a transistor with low leakage current in an off state. As the transistor with low leakage current in an off state, a transistor including an oxide semiconductor layer and a channel formation region included in the oxide semiconductor layer is used.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 15, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Tatsuya Ohnuki
  • Publication number: 20120104480
    Abstract: A storage device in which stored data can be held even when power is not supplied, and stored data can be read at high speed without turning on a transistor included in a storage element is provided. In the storage device, a memory cell having a transistor including an oxide semiconductor layer as a channel region and a storage capacitor is electrically connected to a capacitor to form a node. The voltage of the node is boosted up in accordance with stored data by capacitive coupling through a storage capacitor and the potential is read with an amplifier circuit to distinguish data.
    Type: Application
    Filed: October 25, 2011
    Publication date: May 3, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Daisuke Matsubayashi, Tatsuya Ohnuki
  • Publication number: 20120057397
    Abstract: In a driving method of a semiconductor device which conducts a multilevel writing operation, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. The potential of a bit line is detected while data writing is conducted, and thereby whether a potential corresponding to the written data is normally applied to the floating gate can be confirmed without a writing verify operation.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 8, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Tatsuya Ohnuki
  • Publication number: 20120032164
    Abstract: In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period.
    Type: Application
    Filed: August 2, 2011
    Publication date: February 9, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Tatsuya Ohnuki