Patents by Inventor Tatsuya Ohnuki
Tatsuya Ohnuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9263451Abstract: A storage device in which stored data can be held even when power is not supplied, and stored data can be read at high speed without turning on a transistor included in a storage element is provided. In the storage device, a memory cell having a transistor including an oxide semiconductor layer as a channel region and a storage capacitor is electrically connected to a capacitor to form a node. The voltage of the node is boosted up in accordance with stored data by capacitive coupling through a storage capacitor and the potential is read with an amplifier circuit to distinguish data.Type: GrantFiled: October 25, 2011Date of Patent: February 16, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Daisuke Matsubayashi, Tatsuya Ohnuki
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Patent number: 9263473Abstract: In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period.Type: GrantFiled: July 23, 2014Date of Patent: February 16, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Ohnuki
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Patent number: 9122896Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.Type: GrantFiled: January 24, 2014Date of Patent: September 1, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Ohnuki
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Publication number: 20140332802Abstract: In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period.Type: ApplicationFiled: July 23, 2014Publication date: November 13, 2014Inventor: Tatsuya Ohnuki
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Patent number: 8847627Abstract: A semiconductor device includes a first transistor, a second transistor, a first transistor group, and a second transistor group. The first transistor group includes a third transistor, a fourth transistor, and four terminals. The second transistor group includes fifth to eighth transistors and four terminals. The first transistor, the third transistor, the sixth transistor, and the eighth transistor are n-channel transistors, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are p-channel transistors.Type: GrantFiled: May 16, 2012Date of Patent: September 30, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Ohnuki
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Patent number: 8792284Abstract: In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period.Type: GrantFiled: August 2, 2011Date of Patent: July 29, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Ohnuki
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Publication number: 20140191791Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.Type: ApplicationFiled: January 24, 2014Publication date: July 10, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Ohnuki
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Patent number: 8736371Abstract: To provide a semiconductor device with low power consumption, in a semiconductor device including a differential amplifier to which an input potential and a reference potential are input, a gain stage, and an output stage from which an output potential is output, a potential supplied from the gain stage can be held constant by providing the output stage with a transistor with low leakage current in an off state. As the transistor with low leakage current in an off state, a transistor including an oxide semiconductor layer and a channel formation region included in the oxide semiconductor layer is used.Type: GrantFiled: May 10, 2012Date of Patent: May 27, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Ohnuki
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Patent number: 8638123Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.Type: GrantFiled: May 16, 2012Date of Patent: January 28, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Ohnuki
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Patent number: 8520426Abstract: In a driving method of a semiconductor device which conducts a multilevel writing operation, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. The potential of a bit line is detected while data writing is conducted, and thereby whether a potential corresponding to the written data is normally applied to the floating gate can be confirmed without a writing verify operation.Type: GrantFiled: September 1, 2011Date of Patent: August 27, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya Ohnuki
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Publication number: 20120297221Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.Type: ApplicationFiled: May 16, 2012Publication date: November 22, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Tatsuya Ohnuki
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Publication number: 20120292713Abstract: A semiconductor device includes a first transistor, a second transistor, a first transistor group, and a second transistor group. The first transistor group includes a third transistor, a fourth transistor, and four terminals. The second transistor group includes fifth to eighth transistors and four terminals. The first transistor, the third transistor, the sixth transistor, and the eighth transistor are n-channel transistors, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are p-channel transistors.Type: ApplicationFiled: May 16, 2012Publication date: November 22, 2012Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tatsuya OHNUKI
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Publication number: 20120286871Abstract: To provide a semiconductor device with low power consumption, in a semiconductor device including a differential amplifier to which an input potential and a reference potential are input, a gain stage, and an output stage from which an output potential is output, a potential supplied from the gain stage can be held constant by providing the output stage with a transistor with low leakage current in an off state. As the transistor with low leakage current in an off state, a transistor including an oxide semiconductor layer and a channel formation region included in the oxide semiconductor layer is used.Type: ApplicationFiled: May 10, 2012Publication date: November 15, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Tatsuya Ohnuki
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Publication number: 20120104480Abstract: A storage device in which stored data can be held even when power is not supplied, and stored data can be read at high speed without turning on a transistor included in a storage element is provided. In the storage device, a memory cell having a transistor including an oxide semiconductor layer as a channel region and a storage capacitor is electrically connected to a capacitor to form a node. The voltage of the node is boosted up in accordance with stored data by capacitive coupling through a storage capacitor and the potential is read with an amplifier circuit to distinguish data.Type: ApplicationFiled: October 25, 2011Publication date: May 3, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Daisuke Matsubayashi, Tatsuya Ohnuki
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Publication number: 20120057397Abstract: In a driving method of a semiconductor device which conducts a multilevel writing operation, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. The potential of a bit line is detected while data writing is conducted, and thereby whether a potential corresponding to the written data is normally applied to the floating gate can be confirmed without a writing verify operation.Type: ApplicationFiled: September 1, 2011Publication date: March 8, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Tatsuya Ohnuki
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Publication number: 20120032164Abstract: In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period.Type: ApplicationFiled: August 2, 2011Publication date: February 9, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Tatsuya Ohnuki