Patents by Inventor Tatsuya Oku

Tatsuya Oku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10480693
    Abstract: A threaded joint is constructed of a pin and a box. The pin includes, in order from a tubular body having the pin toward the free end thereof: a male threaded portion and a lip portion including a sealing surface. The box includes: a female threaded portion corresponding to the male threaded portion of the pin; and a recessed portion corresponding to the lip portion, the recessed portion including a sealing surface. The lip portion includes, in order from a male threaded portion toward the free end of the pin: a neck portion; and a sealing head portion including the sealing surface. The maximum outside diameter of the region of the sealing surface in the sealing head portion is larger than an outside diameter of the neck portion at a boundary between the neck portion and the male threaded portion.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: November 19, 2019
    Assignees: NIPPON STEEL CORPORATION, VALLOUREC OIL AND GAS FRANCE
    Inventors: Yousuke Oku, Tatsuya Yamamoto
  • Patent number: 10366876
    Abstract: Provided are a phosphor-containing capable of suppressing deterioration of phosphors and can be manufactured with high efficiency and a backlight unit. Specifically, provided is a phosphor-containing film, including a first substrate film; and a phosphor-containing layer at which a plurality of regions containing phosphors, which, if exposed to oxygen, deteriorate by reacting with the oxygen, are discretely disposed on the first substrate film, and at which a resin layer having an impermeability to oxygen is disposed between the discretely disposed regions containing phosphors, in which a width S of the resin layer between the regions containing phosphors is 0.01?S<0.5 mm, and wherein a ratio of a volume Vp of the regions containing phosphors, to a sum of the volume Vp and a volume Vb of the resin layer in the phosphor-containing layer, is 0.1?Vp/(Vp+Vb)<0.9.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: July 30, 2019
    Assignee: FUJIFILM Corporation
    Inventors: Keisuke Oku, Kenichi Kakishita, Tatsuya Oba
  • Publication number: 20190027626
    Abstract: A laminated sheet of a two-layer sheet in which an L1 layer including 50 to 99 parts by mass of an ethylene-based polymer (E1) having a density of 0.890 to 970 kg/m3 and 1 to 50 parts by mass of a propylene-based polymer (P1) is in contact with an L2 layer including 50 to 100 parts by mass of a propylene-based polymer (P2) and 0 to 50 parts by mass of an ethylene-based elastomer (E2) having a density of equal to or more than 850 kg/m3 and less than 890 kg/m3, in which the propylene-based polymer (P1) includes a propylene-based elastomer (P1a) including a propylene-derived constitutional unit and an ethylene-derived constitutional unit and/or a constitutional unit derived from an ?-olefin having 4 to 20 carbon atoms, and having a melting point (Tm) that is lower than 120° C. or not observable; and a solar cell backsheet formed using the same.
    Type: Application
    Filed: January 12, 2017
    Publication date: January 24, 2019
    Applicant: MITSUI CHEMICALS, INC.
    Inventors: Koya YOSHIMOTO, Kiminori NODA, Makoto EGAWA, Tatsuya OKU
  • Publication number: 20170266934
    Abstract: A laminate film (30) of the present invention includes a heat sealing layer (10) composed of a resin composition including, with respect to 20 to 95 parts by weight of a propylene-based polymer (A) having a melting point (Tm) of equal to or higher than 120° C. and equal to or lower than 170° C. as measured by differential scanning calorimetry (DSC), a total of 5 to 80 parts by weight of two or more kinds of copolymers selected from the group consisting of a propylene.
    Type: Application
    Filed: August 21, 2015
    Publication date: September 21, 2017
    Applicant: MITSUI CHEMICALS, INC.
    Inventors: Tatsuya OKU, Tomohiro ABE, Satoshi IKEDA, Kiminori NODA, Makoto EGAWA
  • Publication number: 20170217144
    Abstract: Disclosed is a stretched laminated film 30 having a heat-sealable layer 10 composed of a resin composition which contains 50 to 97 parts by mass of a propylene-based polymer (A) having a melting point (Tm) of not lower than 120° C. but not higher than 170° C. and comprising more than 50% by mol of a structural unit derived from propylene, 3 to 50 parts by mass of a 1-butene-based polymer (B) having a melting point (Tm) of lower than 120° C. and comprising 10 to 90% by mol of a structural unit derived from 1-butene and 10 to 90% by mol of a structural unit derived from an ?-olefin having 3 or 5 to 20 carbon atoms, and optionally 3 to 30 parts by mass of an ethylene ?-olefin copolymer (C) comprising 50 to 99% by mol of a structural unit derived from ethylene and 1 to 50% by mol of a structural unit derived from an ?-olefin having 3 to 20 carbon atoms, wherein the sum of the component (A) and the component (B) is 100 parts by mass; and a base layer 20.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 3, 2017
    Applicant: MITSUI CHEMICALS, INC.
    Inventors: Tatsuya OKU, Tomohiro ABE, Satoshi IKEDA, Kiminori NODA, Makoto EGAWA
  • Patent number: 8321715
    Abstract: A communication apparatus having a clock interface unit supplying a clock signal for synchronization, includes a clock extracting section for extracting a clock component from a receive signal, a decoding section for generating a decoded signal by decoding in a predetermined encoding form the clock component extracted by the clock extracting section, a frame converting section for creating a receive frame by converting the decoded signal to a frame in a predetermined frame form, a determining section for determining whether the predetermined encoding form and the predetermined frame form are right or not on a basis of the receive frame, a setting section for performing setting regarding the clock signal on a basis of the encoding form and frame form determined to be right by the determining section, and a clock signal output section for outputting the clock signal generated on a basis of the setting by the setting section.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: November 27, 2012
    Assignee: Fujitsu Limited
    Inventors: Tatsuya Oku, Masato Hashizume, Hiroshi Nishida
  • Patent number: 8184665
    Abstract: A disclosed network device includes a plurality of interface cards that receive clock signals and clock signal quality information from other devices via communication lines, respectively being predetermined communication line types corresponding to the plurality of interface cards, a controller that acquires the clock signal quality information and determines one of the clock signals having a highest quality based on this, and a clock processor that generates a synchronization clock signal used for network synchronization the clock processor, based on the determined one of the clock signals, whereby the clock processor includes a frequency measuring instrument that measures a frequency component of the one of the clock signals, and determines the communication line type corresponding to one of the interface cards, and a clock controller that provides a coefficient to a digital filter based on the determined communication line type.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: May 22, 2012
    Assignee: Fujitsu Limited
    Inventors: Tatsuya Oku, Yasuo Takami, Masato Hashizume
  • Publication number: 20100172370
    Abstract: A disclosed network device includes a plurality of interface cards that receive clock signals and clock signal quality information from other devices via communication lines, respectively being predetermined communication line types corresponding to the plurality of interface cards, a controller that acquires the clock signal quality information and determines one of the clock signals having a highest quality based on this, and a clock processor that generates a synchronization clock signal used for network synchronization the clock processor, based on the determined one of the clock signals, whereby the clock processor includes a frequency measuring instrument that measures a frequency component of the one of the clock signals, and determines the communication line type corresponding to one of the interface cards, and a clock controller that provides a coefficient to a digital filter based on the determined communication line type.
    Type: Application
    Filed: November 30, 2009
    Publication date: July 8, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Tatsuya OKU, Yasuo TAKAMI, Masato HASHIZUME
  • Publication number: 20090249107
    Abstract: A communication apparatus having a clock interface unit supplying a clock signal for synchronization, includes a clock extracting section for extracting a clock component from a receive signal, a decoding section for generating a decoded signal by decoding in a predetermined encoding form the clock component extracted by the clock extracting section, a frame converting section for creating a receive frame by converting the decoded signal to a frame in a predetermined frame form, a determining section for determining whether the predetermined encoding form and the predetermined frame form are right or not on a basis of the receive frame, a setting section for performing setting regarding the clock signal on a basis of the encoding form and frame form determined to be right by the determining section, and a clock signal output section for outputting the clock signal generated on a basis of the setting by the setting section.
    Type: Application
    Filed: February 10, 2009
    Publication date: October 1, 2009
    Applicant: Fujitsu Limited
    Inventors: Tatsuya Oku, Masato Hashizume, Hiroshi Nishida
  • Patent number: 7450594
    Abstract: In multi-connections, a message writing apparatus is provided. This message writing apparatus (21) comprises a path recognizing section (21a), a received message assembling section (21b), a receive control section (21c), an arbitrating section (21d) and an external memory control section (21e). When a received ATM cell is written/readout in/from a receiving buffer, it is written/read out in a memory area corresponding to each path, which enables the processing of AAL5 messages from a plurality of paths and improves the transfer processing capability, thereby leading to realizing a shortening of the data transfer time.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: November 11, 2008
    Assignee: Fujitsu Limited
    Inventors: Akira Yamamori, Takeshi Sasaki, Eiji Maeda, Masao Maeda, Tatsuya Oku, Yoshinori Okuda, Tsuguo Okada, Akihiro Yasuo, Jinichi Yoshizawa
  • Patent number: 7027459
    Abstract: Printed circuit boards 11 to 11n are connected in a star-like configuration with a single packet processing IC 42, connected to a CPU 41, at its center, each printed circuit board being connected to the packet processing IC by a high-speed supervisory control line 21 having a sufficient transmission capacity to transfer therethrough transparent information and alarm transfer information as well as information from the central processing unit in packet form, and the transparent information and the alarm transfer information are communicated between the printed circuit boards via the high-speed supervisory control line and via the packet processing IC, with provisions made for the packet processing IC to detect a destination from the packet information received from the originating printed circuit board and to transmit the packet information to the terminating printed circuit board.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: April 11, 2006
    Assignee: Fujitsu Limited
    Inventors: Satoshi Fukui, Tatsuya Oku, Kenji Fukunaga
  • Publication number: 20030072308
    Abstract: Printed circuit boards 11 to 11n are connected in a star-like configuration with a single packet processing IC 42, connected to a CPU 41, at its center, each printed circuit board being connected to the packet processing IC by a high-speed supervisory control line 21 having a sufficient transmission capacity to transfer therethrough transparent information and alarm transfer information as well as information from the central processing unit in packet form, and the transparent information and the alarm transfer information are communicated between the printed circuit boards via the high-speed supervisory control line and via the packet processing IC, with provisions made for the packet processing IC to detect a destination from the packet information received from the originating printed circuit board and to transmit the packet information to the terminating printed circuit board.
    Type: Application
    Filed: February 25, 2002
    Publication date: April 17, 2003
    Inventors: Satoshi Fukui, Tatsuya Oku, Kenji Fukunaga
  • Publication number: 20020057697
    Abstract: In multi-connections, a message writing apparatus is provided. This message writing apparatus (21) comprises a path recognizing section (21a), a received message assembling section (21b), a receive control section (21c), arbitrating section (21d) and an external memory control section (21e). When a received ATM cell is written/readout in/from a receiving buffer, it is written/read out in a memory area corresponding to each path, which enables the processing of AAL5 messages from a plurality of paths and improves the transfer processing capability, thereby leading to realizing a shortening of the data transfer time.
    Type: Application
    Filed: November 9, 2001
    Publication date: May 16, 2002
    Inventors: Akira Yamamori, Takeshi Sasaki, Eiji Maeda, Masao Maeda, Tatsuya Oku, Yoshinori Okuda, Tsuguo Okada, Akihiro Yasuo, Jinichi Yoshizawa
  • Patent number: 5857092
    Abstract: An interface apparatus for SDH/SONET interconnection includes a transmission interface section provided at a position where an apparatus of the SDH system and an apparatus of the SONET system face each other and adapted to transmit a signal toward an apparatus of a different system. The interface apparatus for SDH/SONET interconnection further includes a mode setting unit for setting a mode suitable for an apparatus of a counterpart system, a frame synchronization information inserting unit provided in the transmission interface section and adapted to insert frame synchronization information corresponding to the mode set by the mode setting unit, and an overhead information inserting unit provided in the transmission interface section and adapted to insert overhead information corresponding to the mode set by the mode setting unit. This structure makes is possible to easily interconnect apparatuses of different systems (apparatuses of the SDH system and the SONET system) so as to operate them.
    Type: Grant
    Filed: April 18, 1996
    Date of Patent: January 5, 1999
    Assignee: Fujitsu Limited
    Inventors: Yoshinori Nakamura, Tatsuya Oku, Miki Hagino, Nobuo Iguchi, Hiroaki Mori, Yuuki Tsuji