Patents by Inventor Tatsuya Sakamoto
Tatsuya Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9762108Abstract: Provided is a method for winding an edgewise coil and a winding device capable of saving time and labor when changing a guide. A guide bar is disposed in contact with the side face of the rectangular conductor bent by the bending jig and the rotation center of the guide bar deviates from the rotation center of a bending jig for bending a rectangular conductor. The guide bar rotates in accordance with the action whereby the bending jig bends the rectangular conductor and supports the outside surface of a coil on the side of rotational direction of the bending jig.Type: GrantFiled: April 10, 2013Date of Patent: September 12, 2017Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, NITTOKU ENGINEERING CO., LTD.Inventors: Tatsuya Sakamoto, Yasuyuki Kawanishi
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Publication number: 20150270763Abstract: Provided is a method for winding an edgewise coil and a winding device capable of saving time and labor when changing a guide. A guide bar is disposed in contact with the side face of the rectangular conductor bent by the bending jig and the rotation center of the guide bar deviates from the rotation center of a bending jig for bending a rectangular conductor. The guide bar rotates in accordance with the action whereby the bending jig bends the rectangular conductor and supports the outside surface of a coil on the side of rotational direction of the bending jig.Type: ApplicationFiled: April 10, 2013Publication date: September 24, 2015Applicants: NITTOKU ENGINEERING CO., LTD., TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Tatsuya Sakamoto, Yasuyuki Kawanishi
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Publication number: 20150207056Abstract: Disclosed is an aluminum-magnesium-silicon composite material that contains an alloy comprising Al, Mg, and Si and can be used favorably as a material for a thermoelectric conversion module, and that has excellent thermoelectric conversion properties. The aluminum-magnesium-silicon composite material contains an alloy comprising Al, Mg and Si, and has an electrical conductivity (?) of 1000-3000 S/cm at 300 K. This aluminum-magnesium-silicon composite material is favorable in the production of a thermoelectric exchange element as a result of having excellent thermoelectric conversion properties.Type: ApplicationFiled: March 27, 2015Publication date: July 23, 2015Applicant: Tokyo University of Science Educational Foundation Administrative OrganizationInventors: Tsutomu IIDA, Naoki FUKUSHIMA, Tatsuya SAKAMOTO, Yohiko MITO, Hirokuni NANBA, Yutaka TAGUCHI, Masayasu AKASAKA, Mamoru TACHIKAWA, Takakazu HINO
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Patent number: 8564131Abstract: The invention is characterized in including interconnect layer formed on surface of a substrate forming desired element region, inter layer dielectric covering surface of said interconnect layer, silicon nitride film formed so as covering whole surface of said inter layer dielectric, metal interconnect layer consisting of gold layer as the uppermost lay metal formed on the upper layer of said silicon nitride film, and planarized dielectric formed on said metal interconnect layer.Type: GrantFiled: January 14, 2002Date of Patent: October 22, 2013Assignee: Rohm Co., Ltd.Inventors: Goro Nakatani, Tatsuya Sakamoto
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Patent number: 8199605Abstract: A semiconductor memory integrated circuit having an X-row controller which includes a high-speed-operation control circuit by which when receiving a bank active signal, a period for stopping a latch circuit from receiving the X address is produced after a predetermined time has elapsed, and in the other periods, the latch circuit receives and holds the X address; a low-current-operation control circuit by which when receiving no bank active signal, the latch circuit stops receiving the X address, and when receiving the bank active signal, the latch circuit holds the X address after a predetermined time has elapsed; a circuit for selecting whether the bank active signal is output to the high-speed-operation control circuit or the low-current-operation control circuit; and a circuit for selecting whether the latch-circuit control signal from the high-speed-operation control circuit or the latch-circuit control signal from the low-current-operation control circuit is output to the latch circuit.Type: GrantFiled: August 11, 2009Date of Patent: June 12, 2012Assignee: Elpida Memory, IncInventor: Tatsuya Sakamoto
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Publication number: 20120118343Abstract: Disclosed is an aluminum-magnesium-silicon composite material that contains an alloy comprising Al, Mg, and Si and can be used favorably as a material for a thermoelectric conversion module, and that has excellent thermoelectric conversion properties. The aluminum-magnesium-silicon composite material contains an alloy comprising Al, Mg and Si, and has an electrical conductivity (?) of 1000-3000 S/cm at 300 K. This aluminum-magnesium-silicon composite material is favorable in the production of a thermoelectric exchange element as a result of having excellent thermoelectric conversion properties.Type: ApplicationFiled: July 26, 2010Publication date: May 17, 2012Inventors: Tsutomu Iida, Naoki Fikushima, Tatsuya Sakamoto, Yohiko Mito, Hirokuni Nanba, Yutaka Taguchi, Masayasu Akasaka, Mamoru Tachikawa, Takakazu Hino
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Publication number: 20120097205Abstract: Provided is a magnesium-silicon composite material which contains Mg2Si as an intermetallic compound imposing no burden on the environment, is suitable for use as a material for thermoelectric conversion modules, and has excellent thermoelectric conversion performance. The magnesium-silicon composite material has a dimensionless figure-of-merit parameter at 866K of 0.665 or larger. This magnesium-silicon composite material can have high thermoelectric conversion performance when used in, for example, a thermoelectric conversion module.Type: ApplicationFiled: June 30, 2010Publication date: April 26, 2012Applicant: Tokyo University of Science Educational Foundation Administrative OrganizationInventors: Tsutomu Iida, Yasuhiko Honda, Naoki Fukushima, Tatsuya Sakamoto, Yohiko Mito, Hirokuni Nanba, Yutaka Taguchi
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Patent number: 8130565Abstract: A semiconductor device includes internal voltage generating circuits, a switching circuit, load circuits, a control circuit. Each of the plurality of load circuits is supplied with voltage through the switching circuit from any one of the plurality of internal voltage generating circuits. The control circuit defines connecting combinations by the switch circuit. The control circuit supplies a control signal to the switch circuit, based on the control signal corresponding to the definitions of the connecting combinations. The control circuit allows switching the connecting combinations when the semiconductor device tests in a test mode. The control circuit prohibits switching the connecting combinations in a non-test mode. The switch circuit connects between each of m of the internal voltage generating circuits and each of n of the load circuits through a connecting combination which is selected, based on the control signal, from mn of the connecting combinations.Type: GrantFiled: June 22, 2010Date of Patent: March 6, 2012Assignee: Elpida Memory, Inc.Inventors: Tatsuya Sakamoto, Kanji Oishi, Gen Koshita
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Publication number: 20110316157Abstract: A semiconductor device according to the present invention includes: a semiconductor chip; a sealing resin layer formed on the semiconductor chip; and a post electrode formed in a through-hole penetrating through the sealing resin layer in a thickness direction, and having a hemispheric top surface.Type: ApplicationFiled: September 13, 2011Publication date: December 29, 2011Applicant: ROHM CO., LTD.Inventor: Tatsuya SAKAMOTO
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Patent number: 8072068Abstract: A semiconductor device according to the present invention includes: a semiconductor chip; a sealing resin layer formed on the semiconductor chip; and a post electrode formed in a through-hole penetrating through the sealing resin layer in a thickness direction, and having a hemispheric top surface.Type: GrantFiled: May 20, 2009Date of Patent: December 6, 2011Assignee: Rohm Co., Ltd.Inventor: Tatsuya Sakamoto
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Publication number: 20100327954Abstract: A semiconductor device includes internal voltage generating circuits, a switching circuit, load circuits, a control circuit. Each of the plurality of load circuits is supplied with voltage through the switching circuit from any one of the plurality of internal voltage generating circuits. The control circuit defines connecting combinations by the switch circuit. The control circuit supplies a control signal to the switch circuit, based on the control signal corresponding to the definitions of the connecting combinations. The control circuit allows switching the connecting combinations when the semiconductor device tests in a test mode. The control circuit prohibits switching the connecting combinations in a non-test mode. The switch circuit connects between each of m of the internal voltage generating circuits and each of n of the load circuits through a connecting combination which is selected, based on the control signal, from mn of the connecting combinations.Type: ApplicationFiled: June 22, 2010Publication date: December 30, 2010Applicant: Elpida Memory, Inc.Inventors: Tatsuya Sakamoto, Kanji Oishi, Gen Koshita
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Publication number: 20090296513Abstract: A semiconductor memory integrated circuit having an X-row controller which includes a high-speed-operation control circuit by which when receiving a bank active signal, a period for stopping a latch circuit from receiving the X address is produced after a predetermined time has elapsed, and in the other periods, the latch circuit receives and holds the X address; a low-current-operation control circuit by which when receiving no bank active signal, the latch circuit stops receiving the X address, and when receiving the bank active signal, the latch circuit holds the X address after a predetermined time has elapsed; a circuit for selecting whether the bank active signal is output to the high-speed-operation control circuit or the low-current-operation control circuit; and a circuit for selecting whether the latch-circuit control signal from the high-speed-operation control circuit or the latch-circuit control signal from the low-current-operation control circuit is output to the latch circuit.Type: ApplicationFiled: August 11, 2009Publication date: December 3, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Tatsuya SAKAMOTO
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Publication number: 20090289364Abstract: A semiconductor device according to the present invention includes: a semiconductor chip; a sealing resin layer formed on the semiconductor chip; and a post electrode formed in a through-hole penetrating through the sealing resin layer in a thickness direction, and having a hemispheric top surface.Type: ApplicationFiled: May 20, 2009Publication date: November 26, 2009Applicant: ROHM CO., LTD.Inventor: Tatsuya SAKAMOTO
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Patent number: 7596051Abstract: A semiconductor memory integrated circuit having an X-row controller which includes a high-speed-operation control circuit by which when receiving a bank active signal, a period for stopping a latch circuit from receiving the X address is produced after a predetermined time has elapsed, and in the other periods, the latch circuit receives and holds the X address; a low-current-operation control circuit by which when receiving no bank active signal, the latch circuit stops receiving the X address, and when receiving the bank active signal, the latch circuit holds the X address after a predetermined time has elapsed; a circuit for selecting whether the bank active signal is output to the high-speed-operation control circuit or the low-current-operation control circuit; and a circuit for selecting whether the latch-circuit control signal from the high-speed-operation control circuit or the latch-circuit control signal from the low-current-operation control circuit is output to the latch circuit.Type: GrantFiled: February 5, 2008Date of Patent: September 29, 2009Assignee: Elpida Memory, Inc.Inventor: Tatsuya Sakamoto
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Publication number: 20080198684Abstract: A semiconductor memory integrated circuit having an X-row controller which includes a high-speed-operation control circuit by which when receiving a bank active signal, a period for stopping a latch circuit from receiving the X address is produced after a predetermined time has elapsed, and in the other periods, the latch circuit receives and holds the X address; a low-current-operation control circuit by which when receiving no bank active signal, the latch circuit stops receiving the X address, and when receiving the bank active signal, the latch circuit holds the X address after a predetermined time has elapsed; a circuit for selecting whether the bank active signal is output to the high-speed-operation control circuit or the low-current-operation control circuit; and a circuit for selecting whether the latch-circuit control signal from the high-speed-operation control circuit or the latch-circuit control signal from the low-current-operation control circuit is output to the latch circuit.Type: ApplicationFiled: February 5, 2008Publication date: August 21, 2008Applicant: Elpida Memory, Inc.Inventor: Tatsuya Sakamoto
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Publication number: 20080128904Abstract: A semiconductor device according to the present invention includes a semiconductor chip having an interlayer film provided with an electrode for external connection in a prescribed position, rewiring conducting to the electrode and provided on the interlayer film, an insulating layer covering the rewiring, a pad conducting to the rewiring through an opening formed in the insulating layer and a solder terminal provided on the pad. A photosensitive resin film is provided on the insulating layer. The photosensitive resin film covers the peripheral edge of the interlayer film.Type: ApplicationFiled: November 28, 2007Publication date: June 5, 2008Applicant: ROHM CO., LTD.Inventor: Tatsuya Sakamoto
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Publication number: 20070284721Abstract: A semiconductor device of the present invention is includes a semiconductor device comprising: a semiconductor chip having a passivation film on an electrode forming surface thereof on which a plurality of electrodes are formed; a protective film which is provided on an upper surface of the passivation film and patterned into a predetermined form; rewiring which is provided on an upper surface of each portion of the protective film divided by patterning and is connected to the electrode; a post connected to the rewiring; and a sealing resin layer which covers the rewiring.Type: ApplicationFiled: May 24, 2007Publication date: December 13, 2007Applicant: ROHM CO., LTD.Inventor: Tatsuya Sakamoto
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Patent number: 7238093Abstract: A chemical mechanical polishing cloth for chemically mechanically polishing a workpiece. This chemical mechanical polishing cloth includes, on the opposite-to-workpiece face thereof: polishing projections having polishing faces arranged to come in contact with a workpiece for polishing the same; polishing agent passages for introducing a polishing agent; and at least one-stage step portions formed between the polishing faces of the polishing projections and the bottoms of the polishing agent passages.Type: GrantFiled: December 2, 1999Date of Patent: July 3, 2007Assignee: Rohm Co., Ltd.Inventors: Tatsuya Sakamoto, Muneyuki Matsumoto
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Patent number: 7219933Abstract: A connecting portion (10c) of a container (10) of a catalyst converter is formed with a joining portion (15) to be joined to a joining portion (16) of a flange member (11) by spinning working, and the joining portion (15) formed by the spinning working is joined to the joining portion (16) of the flange member (11) by friction welding. One of the connecting portion (10c) of the container of the catalyst converter and the flange member (11) is extended so as to be disposed radially inward of the joining portions (15) and (16).Type: GrantFiled: May 30, 2001Date of Patent: May 22, 2007Assignee: Toyota Jidosha Kabushiki KaishaInventors: Tatsuya Sakamoto, Seiji Ishizu, Kazushi Wakide
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Patent number: 6880460Abstract: A printing plate is mounted peripherally of a first plate cylinder or a second plate cylinder by using a forward-end clamping mechanism having a forward-end clamping jaw and an air cylinder for opening and closing the forward-end clamping jaw, and a rear-end clamping mechanism having a rear-end clamping jaw and two air cylinders for opening and closing the rear-end clamping jaw. The forward-end clamping mechanism is used for clamping the forward end of the printing plate. The rear-end clamping mechanism is used for clamping the rear end of the printing plate and straining the printing plate over the periphery of the first or second plate cylinder.Type: GrantFiled: March 5, 2003Date of Patent: April 19, 2005Assignee: Dainippon Screen Mfg. Co., Ltd.Inventor: Tatsuya Sakamoto