Patents by Inventor Tatsuya Seino

Tatsuya Seino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5698377
    Abstract: To provide a method of forming a resist pattern in a readily controllable manner and at low costs, in a first exposure step, a resist layer is subject to exposure through a mask. In the next, first developing step, a stepped portion 4 is formed in the resist layer. In a second exposure step, the resist layer is again subject to exposure. At this time, phase shift by 180.degree. occurs in the stepped portion so as to allow some area of the resist layer along the step to be not subject to exposure. In the second developing step, the exposed area of the resist layer 2 is removed to form a resist pattern along the step. Accordingly, the present invention is less subject to diffraction than the case where a phase shifter is employed, and is able to form a resist pattern in a readily controllable manner and reduce fabrication costs.
    Type: Grant
    Filed: June 11, 1996
    Date of Patent: December 16, 1997
    Assignee: Nippon Precision Circuits Inc.
    Inventor: Tatsuya Seino
  • Patent number: 5683933
    Abstract: To minimize error in size and form a thick oxide layer as field insulating means in a narrow isolation region, a method of fabricating a semiconductor device is carried out as followings.A polysilicon layer 3 is formed on a silicon substrate 1. A silicon nitride layer 5 is then formed on the polysilicon layer 3. Thereafter, an aperture 7 is formed in the silicon nitride layer 5 and reaches the polysilicon layer. A silicon layer 9 is formed in the aperture 7 by epitaxial growth technique. The silicon layer 9 is selectively oxidized to form an oxide layer 10 as field insulating means. The silicon nitride layer 5 and a portion of the polysilicon layer 3 which was left unoxidized are removed. This makes it possible to form the desired thick oxide layer as field insulating means in a narrow region.
    Type: Grant
    Filed: June 17, 1996
    Date of Patent: November 4, 1997
    Assignee: Nippon Precision Circuits Inc.
    Inventor: Tatsuya Seino