Abstract: An information processing system includes a plurality of control apparatuses communicably coupled to each other. A first control apparatus of the plurality of control apparatuses includes a first memory configured to store first instructions and a first processor configured to operate using standby power before a power-on selection is made. The first processor executes the first instructions causing a process including collecting first identification information of each of the plurality of control apparatuses other than the first control apparatus. The process includes storing the first identification information in the first memory. The process includes determining a role of the first control apparatus based on a comparison result derived by comparing second identification information of the first control apparatus with the first identification information.

Abstract: An information processing system includes a plurality of control apparatuses communicably coupled to each other. A first control apparatus of the plurality of control apparatuses includes a first memory configured to store first instructions and a first processor configured to operate using standby power before a power-on selection is made. The first processor executes the first instructions causing a process including collecting first identification information of each of the plurality of control apparatuses other than the first control apparatus. The process includes storing the first identification information in the first memory. The process includes determining a role of the first control apparatus based on a comparison result derived by comparing second identification information of the first control apparatus with the first identification information.

Abstract: An information processing apparatus includes: an interface unit that communicates with another device through a plurality of physical links; a setting unit that determines a value of a setting parameter for setting a signal transmission characteristic for each of the plurality of physical links by performing a negotiation with the other device and that outputs a plurality of determined values of the setting parameter, each of the plurality of determined values corresponding to one of the plurality of physical links; and a judgment unit that judges whether each of the plurality of determined values is correct or not by judging whether or not a difference between a maximum value and a minimum value among the plurality of determined values falls within a predetermined range.

Abstract: A control device includes a first memory, a first processor coupled to the first memory, a second memory, and a second processor coupled to the second memory. The first processor is configured to store log information of an information processing device into the first memory. The second processor is configured to determine whether the log information is stored in the first memory. The second processor is configured to read the log information from the first memory when the second processor determines that the log information is stored in the first memory. The second processor is configured to write the read log information into the second memory.

Abstract: An information processing apparatus includes: an interface unit that communicates with another device through a plurality of physical links; a setting unit that determines a value of a setting parameter for setting a signal transmission characteristic for each of the plurality of physical links by performing a negotiation with the other device and that outputs a plurality of determined values of the setting parameter, each of the plurality of determined values corresponding to one of the plurality of physical links; and a judgment unit that judges whether each of the plurality of determined values is correct or not by judging whether or not a difference between a maximum value and a minimum value among the plurality of determined values falls within a predetermined range.

Abstract: An information processing apparatus includes a processor, a memory, and a cache. Information read from the memory by the processor is stored in the cache. The processor writes the information stored in the memory in all of the regions of the cache at a predetermined timing.