Patents by Inventor Tatsuya Sugimachi
Tatsuya Sugimachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180102373Abstract: A semiconductor device includes: a semiconductor substrate; a ferroelectric capacitor above the semiconductor substrate; a first guard ring around the ferroelectric capacitor above the semiconductor substrate. The ferroelectric capacitor includes a bottom electrode, a capacitor insulating film and a top electrode. The first guard ring includes a first pseudo bottom electrode, a first pseudo capacitor insulating film and a first pseudo top electrode, and surrounds the ferroelectric capacitors in planar view.Type: ApplicationFiled: December 8, 2017Publication date: April 12, 2018Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Naoya SASHIDA, Tatsuya SUGIMACHI
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Publication number: 20160093627Abstract: A semiconductor device includes: a semiconductor substrate; a ferroelectric capacitor above the semiconductor substrate; a first guard ring around the ferroelectric capacitor above the semiconductor substrate. The ferroelectric capacitor includes a bottom electrode, a capacitor insulating film and a top electrode. The first guard ring includes a first pseudo bottom electrode, a first pseudo capacitor insulating film and a first pseudo top electrode, and surrounds the ferroelectric capacitors in planar view.Type: ApplicationFiled: August 20, 2015Publication date: March 31, 2016Inventors: Naoya SASHIDA, TATSUYA SUGIMACHI
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Patent number: 9287277Abstract: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.Type: GrantFiled: July 6, 2012Date of Patent: March 15, 2016Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Tatsuya Sugimachi, Satoshi Torii
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Patent number: 8865536Abstract: As for a bypass capacitor, a first capacitor insulating film, together with a tunnel insulating film of a storage element, is formed of a first insulating film, a first electrode being a lower electrode, together with floating gate electrodes of the storage element, is formed of a doped·amorphous silicon film (a crystallized one), a second capacitor insulating film, together with a gate insulating film of transistors of 5 V in a peripheral circuit, is formed of a second insulating film, and a second electrode being an upper electrode, together with control gate electrodes of the storage element and gate electrodes of the transistors in the peripheral circuit, is formed of a polycrystalline silicon film.Type: GrantFiled: June 28, 2011Date of Patent: October 21, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Tatsuya Sugimachi
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Patent number: 8604533Abstract: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.Type: GrantFiled: August 7, 2009Date of Patent: December 10, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Tatsuya Sugimachi, Satoshi Torii
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Publication number: 20120270373Abstract: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.Type: ApplicationFiled: July 6, 2012Publication date: October 25, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Tatsuya SUGIMACHI, Satoshi TORII
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Publication number: 20120074478Abstract: As for a bypass capacitor, a first capacitor insulating film, together with a tunnel insulating film of a storage element, is formed of a first insulating film, a first electrode being a lower electrode, together with floating gate electrodes of the storage element, is formed of a doped·amorphous silicon film (a crystallized one), a second capacitor insulating film, together with a gate insulating film of transistors of 5 V in a peripheral circuit, is formed of a second insulating film, and a second electrode being an upper electrode, together with control gate electrodes of the storage element and gate electrodes of the transistors in the peripheral circuit, is formed of a polycrystalline silicon film.Type: ApplicationFiled: June 28, 2011Publication date: March 29, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Tatsuya Sugimachi
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Publication number: 20100032745Abstract: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.Type: ApplicationFiled: August 7, 2009Publication date: February 11, 2010Applicant: FUJITSU MICROELECTRONICS Ltd.Inventors: Tatsuya Sugimachi, Satoshi Torii
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Patent number: 6239500Abstract: A field insulating film defines a plurality of active regions disposed regularly in terms of two dimension on the surface of a semiconductor substrate. Each active region includes one bit contact region and subsidiary active regions extending from the bit contact region in four directions. A plurality of first word lines are formed which extend as a whole in a first direction on the semiconductor substrate, and a plurality of second word lines are formed which extend as a whole in a second direction on the semiconductor substrate, crossing the first word lines. Two subsidiary active regions cross the first word lines and remaining two subsidiary active regions cross the second word lines. A plurality of bit lines are formed which extend as a whole in the first and second directions on the semiconductor substrate, crossing each other. Each bit contact region is connected to a corresponding one of the bit lines. Four transistors share one bit contact, and these four transistors have different word lines.Type: GrantFiled: August 26, 1999Date of Patent: May 29, 2001Assignee: Fujitsu LimitedInventor: Tatsuya Sugimachi