Abstract: A memory system of one embodiment includes: a nonvolatile memory including a plurality of word lines each connected to memory cells, each one of the memory cells being capable storing two bits, the memory cells connected to one of the plurality of word lines constituting an upper page and a lower page, each one of the pages being a unit of data programming; a random access memory configured to store an address translation table indicating relationships between logical addresses designated by a host and physical addresses in the nonvolatile memory. The memory system of the embodiment further includes a memory controller which execute data fixing for saving the address translation table from the random access memory to the nonvolatile memory; and write dummy data to at least one page subsequent to the page in which valid data has been written in the nonvolatile memory before executing the data fixing.

Abstract: In a semiconductor memory device of an embodiment, a backup section writes backup data to a memory. The backup data corresponds to management data which associates identification data of data written to the memory with a write position of the data. A first generator generates update data indicating an updating state when the management data is updated after the backup data is written to the memory. A second generator generates update accumulated data including the update data and past update data which has been generated before the update data and written to the memory. A writer writes the update accumulated data to the memory. A restoration section restores the management data based on the backup data read from the memory and the update accumulated data.

Abstract: A management information generating method wherein logical and physical block addresses (BAs) of continuous addresses are associated with each other in the BA translation table. When a logical block is constructed, a value is set for a maximum number of allowable defective physical blocks. A logical block having fewer defects than the set number is set usable, and a logical block having more defects than the set number is set unusable. System logical block construction is performed to preferentially select physical blocks from a plane list including a large number of usable blocks to equalize the number of usable blocks in each plane list. It is determined whether the number of free blocks is insufficient on the basis of a first management unit and whether the storage area for the indicated capacity can be reserved on the basis of the management unit different from the first unit.

Abstract: A management information generating method wherein logical and physical block addresses (BAs) of continuous addresses are associated with each other in the BA translation table. When a logical block is constructed, an allowable value is set for the number of defective physical blocks. A logical block having fewer defects than the set number is set usable, and a logical block having more defects than the set number is set unusable. System logical block construction is performed to preferentially select physical blocks from a plane list including a large number of usable blocks to equalize the number of usable blocks in each plane list. It is determined whether the number of free blocks is insufficient on the basis of a first management unit and whether the storage area for the indicated capacity can be reserved on the basis of the management unit different from the first unit.

Abstract: According to one embodiment, a free blocks included in a nonvolatile semiconductor memory are classified into a plurality of free block management lists. When a free block is acquired at normal priority, the free block is acquired from the free block management list in which a number of free blocks is larger than a first threshold. When a free block is acquired at high priority, the free block is acquired from the free block management list irrespective of the first threshold.

Abstract: A memory system of one embodiment includes: a nonvolatile memory including a plurality of word lines each connected to memory cells, each one of the memory cells being capable storing two bits, the memory cells connected to one of the plurality of word lines constituting an upper page and a lower page, each one of the pages being a unit of data programming; a random access memory configured to store an address translation table indicating relationships between logical addresses designated by a host and physical addresses in the nonvolatile memory. The memory system of the embodiment further includes a memory controller which execute data fixing for saving the address translation table from the random access memory to the nonvolatile memory; and write dummy data to at least one page subsequent to the page in which valid data has been written in the nonvolatile memory before executing the data fixing.

Abstract: According to one embodiment, a free blocks included in a nonvolatile semiconductor memory are classified into a plurality of free block management lists. When a free block is acquired at normal priority, the free block is acquired from the free block management list in which a number of free blocks is larger than a first threshold. When a free block is acquired at high priority, the free block is acquired from the free block management list irrespective of the first threshold.