Patents by Inventor Tatsuya Tanabe
Tatsuya Tanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240124389Abstract: An object of present invention is to provide a compound or a salt thereof constituting lipid particles that can achieve a high nucleic acid encapsulation rate and excellent delivery of nucleic acids, and to provide lipid particles and pharmaceutical composition using the compound or a salt thereof, which can achieve a high nucleic acid encapsulation rate and excellent delivery of nucleic acids. According to an aspect of the present invention, a compound represented by Formula (1) or a salt thereof is provided. In the formula, each symbol has a meaning defined in the present specification.Type: ApplicationFiled: October 26, 2023Publication date: April 18, 2024Applicant: FUJIFILM CorporationInventors: Shintaro TANABE, Tatsuya NITABARU, Mashiko YAMAMOTO, Hirofumi FUKUNAGA, Naoto NAKAMURA, Noriyuki KASAGI, Taisuke ENDO, Keiko SUZUKI
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Publication number: 20240128081Abstract: A film forming method includes preparing a substrate having an amorphous silicon film on a surface thereof, diffusing nickel into the amorphous silicon film by supplying a nickel source gas to the amorphous silicon film, and forming a polycrystalline silicon film by heating the amorphous silicon film, and crystallizing the amorphous silicon film by metal-induced lateral crystallization using the nickel diffused in the amorphous silicon film as a nucleus.Type: ApplicationFiled: October 5, 2023Publication date: April 18, 2024Inventors: Yoshihiro TAKEZAWA, Toru KANAZAWA, Yosuke WATANABE, Tatsuya MIYAHARA, Yuki TANABE, Daisuke SUZUKI, Masahisa WATANABE, Keisuke SUZUKI, Tuhin Shuvra Basu
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Patent number: 8633514Abstract: A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlXGa1-XN (0<X?1), a first AlGaN layer made of group III nitride-based semiconductor containing Al and disposed on the substrate, and a second AlGaN layer made of group III nitride-based semiconductor having a bandgap greater than the first AlGaN layer and disposed thereon. The full width at half maximum values of X-ray rocking curves for (0002) and (10-12) planes of the first AlGaN layer are less than 1000 arcseconds.Type: GrantFiled: March 1, 2012Date of Patent: January 21, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Hashimoto, Tatsuya Tanabe, Katsushi Akita, Hideaki Nakahata, Hiroshi Amano
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Patent number: 8541816Abstract: In a group III nitride hetero junction transistor 11a, a second AlY1InY2Ga1-Y1-Y2N layer 15 forms a hetero junction 21 with a first AlX1InX2Ga1-X1-X2N layer 13a. A first electrode 17 forms a Schottky junction with the first AlX1InX2Ga1-X1-X2N layer 13a. The first AlX1InX2Ga1-X1-X2N layer 13a and the second AlY1InY2Ga1-Y1-Y2N layer 15 are provided over a substrate 23. The electrodes 17a, 18a, and 19a include a source electrode, a gate electrode, and a drain electrode, respectively. The carbon concentration NC13 in the first AlX1InX2Ga1-X1-X2N layer 13a is less than 1×1017 cm?3. The dislocation density D in the second AlY1InY2Ga1-Y1-Y2N layer 15 is 1×108 cm?2. The hetero junction 21 generates a two-dimensional electron gas layer 25. These provide a low-loss gallium nitride based electronic device.Type: GrantFiled: October 28, 2008Date of Patent: September 24, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Hashimoto, Tatsuya Tanabe
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Patent number: 8461570Abstract: A method for manufacturing a semiconductor device, by which a multiple quantum well structure having a large number of pairs can be efficiently grown while maintaining good crystalline quality, and the semiconductor device, are provided. The semiconductor device manufacturing method of the present invention includes a step of forming a multiple quantum well structure 3 having 50 or more pairs of group III-V compound semiconductor quantum wells. In the step of forming the multiple quantum well structure 3, the multiple quantum well structure is formed by metal-organic vapor phase epitaxy using only metal-organic sources (all metal-organic source MOVPE).Type: GrantFiled: July 7, 2010Date of Patent: June 11, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kei Fujii, Takashi Ishizuka, Katsushi Akita, Youichi Nagai, Tatsuya Tanabe
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Patent number: 8410524Abstract: Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be reduced. In a high electron mobility transistor 11, a supporting substrate 13 is composed of AlN, AlGaN, or GaN, specifically. An AlYGa1?YN epitaxial layer 15 has a full-width-at-half maximum of (0002) plane XRD of 150 sec or less. A GaN epitaxial layer 17 is provided between the gallium nitride supporting substrate and the AlYGa1?YN epitaxial layer (0<Y?1). A Schottky electrode 19 is provided on the AlYGa1?YN epitaxial layer 15. The Schottky electrode 19 constitutes a gate electrode of the high electron mobility transistor 11. The source electrode 21 is provided on the gallium nitride epitaxial layer 15. The drain electrode 23 is provided on the gallium nitride epitaxial layer 15.Type: GrantFiled: March 6, 2006Date of Patent: April 2, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Tatsuya Tanabe, Kouhei Miura, Makoto Kiyama, Takashi Sakurada
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Patent number: 8404571Abstract: Provided is a film deposition method capable of improving the crystal characteristic near an interface according to the lattice constant of a material that will constitute a thin film to be deposited. Specifically, a substrate is curved relative to the direction along one main surface on which the thin film is to be deposited, according to the lattice constant the material that will constitute the thin film to be deposited and the lattice constant of a material constituting the one main surface. The thin film is deposited on the one main surface of the substrate with the substrate curved.Type: GrantFiled: June 25, 2009Date of Patent: March 26, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Hashimoto, Tatsuya Tanabe
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Publication number: 20120161205Abstract: A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlXGa1-XN (0<X?1), a first AlGaN layer made of group III nitride-based semiconductor containing Al and disposed on the substrate, and a second AlGaN layer made of group III nitride-based semiconductor having a bandgap greater than the first AlGaN layer and disposed thereon. The full width at half maximum values of X-ray rocking curves for (0002) and (10-12) planes of the first AlGaN layer are less than 1000 areseconds.Type: ApplicationFiled: March 1, 2012Publication date: June 28, 2012Applicant: Sumitomo Electric Industries, Ltd.Inventors: Shin HASHIMOTO, Tatsuya Tanabe, Katsushi Akita, Hideaki Nakahata, Hiroshi Amano
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Patent number: 8148751Abstract: A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlXGa1-XN (0<X?1), a first AlGaN layer made of group III nitride-based semiconductor containing Al and disposed on the substrate, and a second AlGaN layer made of group III nitride-based semiconductor having a bandgap greater than the first AlGaN layer and disposed thereon. The full width at half maximum values of X-ray rocking curves for (0002) and (10-12) planes of the first AlGaN layer are less than 1000 arcseconds.Type: GrantFiled: March 26, 2010Date of Patent: April 3, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Hashimoto, Tatsuya Tanabe, Katsushi Akita, Hideaki Nakahata, Hiroshi Amano
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Publication number: 20120006263Abstract: When a film is to be deposited on a semiconductor substrate or the like in a heating ambient, the semiconductor substrate is caused to warp (curve) to a considerable extent merely due to an increased temperature. The warpage leads to problems such as degradation of the homogeneity of the quality of the film deposited on the substrate and a high possibility of generation of a crack in the substrate. Accordingly, a film deposition apparatus of the present invention heats the substrate both from above and from below a main surface of the substrate so that a temperature gradient (temperature difference) between the upper side and the lower side of the main surface is reduced and the warpage of the substrate is suppressed. More preferably a measurement unit for measuring the curvature or warpage of the substrate is included.Type: ApplicationFiled: August 6, 2009Publication date: January 12, 2012Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shin Hashimoto, Tatsuya Tanabe
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Publication number: 20110210313Abstract: A method for manufacturing a semiconductor device, by which a multiple quantum well structure having a large number of pairs can be efficiently grown while maintaining good crystalline quality, and the semiconductor device, are provided. The semiconductor device manufacturing method of the present invention includes a step of forming a multiple quantum well structure 3 having 50 or more pairs of group III-V compound semiconductor quantum wells. In the step of forming the multiple quantum well structure 3, the multiple quantum well structure is formed by metal-organic vapor phase epitaxy using only metal-organic sources (all metal-organic source MOVPE).Type: ApplicationFiled: July 7, 2010Publication date: September 1, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kei Fujii, Takashi Ishizuka, Katsushi Akita, Youichi Nagai, Tatsuya Tanabe
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Publication number: 20110097880Abstract: Provided is a film deposition method capable of improving the crystal characteristic near an interface according to the lattice constant of a material that will constitute a thin film to be deposited. Specifically, a substrate is curved relative to the direction along one main surface on which the thin film is to be deposited, according to the lattice constant the material that will constitute the thin film to be deposited and the lattice constant of a material constituting the one main surface. The thin film is deposited on the one main surface of the substrate with the substrate curved.Type: ApplicationFiled: June 25, 2009Publication date: April 28, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shin Hashimoto, Tatsuya Tanabe
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Publication number: 20110049573Abstract: A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlXGa1?XN (0<X?1), a first AlGaN layer made of group III nitride-based semiconductor containing Al and disposed on the substrate, and a second AlGaN layer made of group III nitride-based semiconductor having a bandgap greater than the first AlGaN layer and disposed thereon. The full width at half maximum values of X-ray rocking curves for (0002) and (10-12) planes of the first AlGaN layer are less than 1000 arcseconds.Type: ApplicationFiled: March 26, 2010Publication date: March 3, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shin HASHIMOTO, Tatsuya TANABE, Katsushi AKITA, Hideaki NAKAHATA, Hiroshi AMANO
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Patent number: 7884393Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor (11) is provided with a supporting substrate (13) composed of gallium nitride, a buffer layer (15) composed of a first gallium nitride semiconductor, a channel layer (17) composed of a second gallium nitride semiconductor, a semiconductor layer (19) composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode (21), a source electrode (23) and a drain electrode (25) for the transistor (11). The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm?3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm?3.Type: GrantFiled: May 25, 2010Date of Patent: February 8, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Hashimoto, Makoto Kiyama, Takashi Sakurada, Tatsuya Tanabe, Kouhei Miura, Tomihito Miyazaki
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Patent number: 7872285Abstract: Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm?3 or more. The donor impurity is at least either silicon or germanium.Type: GrantFiled: March 1, 2006Date of Patent: January 18, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Hashimoto, Makoto Kiyama, Tatsuya Tanabe, Kouhei Miura, Takashi Sakurada
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Publication number: 20100230687Abstract: In a group III nitride hetero junction transistor 11a, a second AlY1InY2Ga1-Y1-Y2N layer 15 forms a hetero junction 21 with a first AlX1InX2Ga1-X1-X2N layer 13a. A first electrode 17 forms a Schottky junction with the first AlX1InX2Ga1-X1-X2N layer 13a. The first AlX1InX2Ga1-X1-X2N layer 13a and the second AlY1InY2Ga1-Y1-Y2N layer 15 are provided over a substrate 23. The electrodes 17a, 18a, and 19a include a source electrode, a gate electrode, and a drain electrode, respectively. The carbon concentration NC13 in the first AlX1InX2Ga1-X1-X2N layer 13a is less than 1×1017 cm?3. The dislocation density D in the second AlY1InY2Ga1-Y1-Y2N layer 15 is 1×108 cm?2. The hetero junction 21 generates a two-dimensional electron gas layer 25. These provide a low-loss gallium nitride based electronic device.Type: ApplicationFiled: October 28, 2008Publication date: September 16, 2010Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shin Hashimoto, Tatsuya Tanabe
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Publication number: 20100230723Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor (11) is provided with a supporting substrate (13) composed of gallium nitride, a buffer layer (15) composed of a first gallium nitride semiconductor, a channel layer (17) composed of a second gallium nitride semiconductor, a semiconductor layer (19) composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode (21), a source electrode (23) and a drain electrode (25)) for the transistor (11). The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm?3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm?3.Type: ApplicationFiled: May 25, 2010Publication date: September 16, 2010Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shin Hashimoto, Makoto Kiyama, Takashi Sakurada, Tatsuya Tanabe, Kouhei Miura, Tomihito Miyazaki
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Patent number: 7749828Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a second gallium nitride semiconductor, a semiconductor layer 19 composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode 21, a source electrode 23 and a drain electrode 25) for the transistor 11. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm?3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm?3.Type: GrantFiled: March 3, 2006Date of Patent: July 6, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Hashimoto, Makoto Kiyama, Takashi Sakurada, Tatsuya Tanabe, Kouhei Miura, Tomihito Miyazaki
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Publication number: 20090194796Abstract: Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm?3 or more. The donor impurity is at least either silicon or germanium.Type: ApplicationFiled: March 1, 2006Publication date: August 6, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shin Hashimoto, Makoto Kiyama, Tatsuya Tanabe, Kouhei Miura, Takashi Sakurada
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Publication number: 20090189186Abstract: Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be reduced. In a high electron mobility transistor 11, a supporting substrate 13 is composed of AlN, AlGaN, or GaN, specifically. An AlYGa1?YN epitaxial layer 15 has a full-width-at-half maximum of (0002) plane XRD of 150 sec or less. A GaN epitaxial layer 17 is provided between the gallium nitride supporting substrate and the AlYGa1?YN epitaxial layer (O<Y?1). A Schottky electrode 19 is provided on the AlYGa1?YN epitaxial layer 15. The Schottky electrode 19 constitutes a gate electrode of the high electron mobility transistor 11. The source electrode 21 is provided on the gallium nitride epitaxial layer 15. The drain electrode 23 is provided on the gallium nitride epitaxial layer 15.Type: ApplicationFiled: March 6, 2006Publication date: July 30, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Tatsuya Tanabe, Kouhei Miura, Makoto Kiyama, Takashi Sakurada