Patents by Inventor Tatsuya TODA

Tatsuya TODA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953610
    Abstract: Movement information is calculated with high accuracy, without being influenced by the number of GNSS signals receivable by each of a plurality of antennas. A movement information calculating device includes a plurality of antennas, a clock generator, a plurality of GNSS receivers, and an arithmetic logical unit. The plurality of antennas, each receives a GNSS signal. The clock generator generates a clock signal. The plurality of GNSS receivers are connected to the respective antennas, and share the clock signal from the clock generator and calculate GNSS observed values by using the shared clock signal and the GNSS signals, respectively. The arithmetic logical unit calculates movement information including a speed of a movable body based on the GNSS observed values from the plurality of GNSS receivers.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: April 9, 2024
    Assignee: Furuno Electric Co., Ltd.
    Inventors: Tatsuya Sonobe, Hiraku Nakamura, Hiroyuki Toda
  • Publication number: 20240092044
    Abstract: A molding drum is provided in which a sheet-shaped rubber member for a tire is wound around an outer circumferential surface having a cylindrical shape. A plurality of segments are arranged in a drum circumferential direction, and the outer circumferential surface of the molding drum is formed by outer surfaces of the segments coinciding with each other. At least one of the plurality of segments is a tip-end holding segment including at least a first small segment and a second small segment that serve as small segments arranged in the drum circumferential direction. The first small segment can take a first state in which an outer surface of the first small segment coincides with an outer surface of the second small segment, and a second state in which at least a portion of the first small segment is disposed outward of the second small segment in a drum radial direction.
    Type: Application
    Filed: July 31, 2023
    Publication date: March 21, 2024
    Applicant: Toyo Tire Corporation
    Inventor: Tatsuya Toda
  • Patent number: 11935898
    Abstract: A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 19, 2024
    Assignee: Japan Display Inc.
    Inventors: Tatsuya Toda, Toshinari Sasaki, Masayoshi Fuchi
  • Patent number: 11927859
    Abstract: A display device comprising a transistor and a display element over the transistor, wherein the transistor includes a gate electrode on an insulating surface, a gate insulating layer on the gate electrode, and source/drain electrodes on the oxide semiconductor layer and the gate insulating layer, each including a first conductive layer containing nitrogen and a second conductive layer on the first conductive layer, and an insulating layer contains oxygen on the oxide semiconductor layer and the source/drain electrodes.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: March 12, 2024
    Assignee: Japan Display Inc.
    Inventors: Masashi Tsubuku, Takeshi Sakai, Tatsuya Toda
  • Publication number: 20230187558
    Abstract: A semiconductor device includes a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor film via the gate insulating film on the gate electrode, a source electrode and a drain electrode on the oxide semiconductor film, a protective film provided on the source electrode and the drain electrode; and a conductive layer provided on the protective film and overlapped on the oxide semiconductor layer. The protective film includes a first silicon oxide film and a first silicon nitride film. The first oxide film is in contact with the oxide semiconductor layer. The gate insulating film includes a second silicon nitride film and a second silicon oxide film. The second silicon oxide film is in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region located between the source electrode and the drain electrode in a plan view.
    Type: Application
    Filed: February 1, 2023
    Publication date: June 15, 2023
    Applicant: Japan Display Inc.
    Inventors: Masashi TSUBUKU, Michiaki SAKAMOTO, Takashi OKADA, Toshiki KANEKO, Tatsuya TODA
  • Patent number: 11594641
    Abstract: A semiconductor device includes a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor film via the gate insulating film on the gate electrode, a source electrode and a drain electrode on the oxide semiconductor film, a protective film provided on the source electrode and the drain electrode; and a conductive layer provided on the protective film and overlapped on the oxide semiconductor layer. The protective film includes a first silicon oxide film and a first silicon nitride film. The first oxide film is in contact with the oxide semiconductor layer. The gate insulating film includes a second silicon nitride film and a second silicon oxide film. The second silicon oxide film is in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region located between the source electrode and the drain electrode in a plan view.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: February 28, 2023
    Assignee: Japan Display Inc.
    Inventors: Masashi Tsubuku, Michiaki Sakamoto, Takashi Okada, Toshiki Kaneko, Tatsuya Toda
  • Publication number: 20230018290
    Abstract: A cutting tool (1) formed of a silicon nitride-based sintered body (2) including a matrix phase (3), a hard phase (4), and a grain boundary phase (10) in which a glass phase (11) and a crystal phase (12) exist. The sintered body (2) contains yttrium in an amount of 5.0 wt % to 15.0 wt % in terms of an oxide, and contains titanium nitride as the hard phase (4) in an amount of 5.0 wt % to 25.0 wt %. In an X-ray diffraction peak, a halo pattern appears at 2? ranging from 25° to 35° in an internal region of the sintered body (2). A ratio B/A of a maximum peak intensity B to a maximum peak intensity A satisfies 0.11?B/A?0.40 . . . Expression (1) in a surface region of the sintered body (2), and satisfies 0.00?B/A?0.10 . . . Expression (2) in the internal region of the sintered body (2).
    Type: Application
    Filed: October 28, 2020
    Publication date: January 19, 2023
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventors: Tatsuya TODA, Takuya FURUHASHI, Ryoji TOYODA
  • Patent number: 11342463
    Abstract: A semiconductor device comprising: an oxide semiconductor layer including indium; a gate electrode facing to the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and the gate electrode; a first conductive layer arranged above the oxide semiconductor layer and being in contact with the oxide semiconductor layer from above the oxide semiconductor layer; an oxide portion formed on the oxide semiconductor layer and at an edge of the first conductive layer, the oxide portion being a oxide of the first conductive layer.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: May 24, 2022
    Assignee: Japan Display Inc.
    Inventors: Tatsuya Toda, Masashi Tsubuku
  • Publication number: 20220013668
    Abstract: A semiconductor device includes an oxide semiconductor layer including indium, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, and a first electrode arranged above the oxide semiconductor layer and being in contact with the oxide semiconductor layer from above the oxide semiconductor layer. The indium is unevenly distributed in an unevenly distributed region among the oxide semiconductor layer. The unevenly distributed region overlaps with the first conductive layer in a planar view.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Applicant: Japan Display Inc.
    Inventors: Tatsuya TODA, Masashi TSUBUKU, Toshinari SASAKI
  • Publication number: 20220004039
    Abstract: A display device comprising a transistor and a display element over the transistor, wherein the transistor includes a gate electrode on an insulating surface, a gate insulating layer on the gate electrode, and source/drain electrodes on the oxide semiconductor layer and the gate insulating layer, each including a first conductive layer containing nitrogen and a second conductive layer on the first conductive layer, and an insulating layer contains oxygen on the oxide semiconductor layer and the source/drain electrodes.
    Type: Application
    Filed: September 15, 2021
    Publication date: January 6, 2022
    Applicant: Japan Display Inc.
    Inventors: Masashi TSUBUKU, Takeshi SAKAI, Tatsuya TODA
  • Publication number: 20210210524
    Abstract: To reduce degradation of characteristics and reliability of a transistor including an oxide semiconductor as an active layer. A thin film transistor comprising: an active layer formed of an oxide semiconductor including at least indium and gallium; an electrode layer including an aluminum layer and partially formed on the active layer; and an interlayer insulating layer formed on the active layer, wherein a peak value of chlorine concentration at an interface between the interlayer insulating layer and the active layer is equal to or less than 2.0×1019 [atoms/cm3], and a peak value of aluminum concentration at an interface between the interlayer insulating layer and the active layer is equal to or less than 1.0×1020 [atoms/cm3].
    Type: Application
    Filed: March 23, 2021
    Publication date: July 8, 2021
    Applicant: Japan Display Inc.
    Inventors: Tatsuya TODA, Masashi TSUBUKU
  • Publication number: 20210202639
    Abstract: To sufficiently reduce an off-leakage current of a transistor including an oxide semiconductor as an active layer, provide a transistor having uniform characteristics when forming a large number of transistors on a large substrate, and reduce a load on a manufacturing process. A thin film transistor comprising: an active layer formed of an oxide semiconductor including at least indium and gallium; a gate electrode; a first gate insulating layer disposed between the active layer and the gate electrode on the gate electrode side; and a second gate insulating layer, which is a hydrogen block layer, disposed between the active layer and the gate electrode on the active layer side.
    Type: Application
    Filed: March 12, 2021
    Publication date: July 1, 2021
    Applicant: Japan Display Inc.
    Inventors: Masashi TSUBUKU, Tatsuya TODA
  • Publication number: 20210151576
    Abstract: A thin film transistor comprising an active layer made of an oxide semiconductor containing indium and gallium, an electrode layer including a titanium layer formed on the active layer, wherein an indium concentration is equal to or less than 1.3 times an oxygen concentration in a range of 15 nm from an interface between the active layer and the electrode layer toward the active layer.
    Type: Application
    Filed: January 29, 2021
    Publication date: May 20, 2021
    Inventors: Takeshi SAKAI, Tatsuya TODA, Masashi TSUBUKU
  • Publication number: 20210119055
    Abstract: A semiconductor device comprising: an oxide semiconductor layer including indium; a gate electrode facing to the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and the gate electrode; a first conductive layer arranged above the oxide semiconductor layer and being in contact with the oxide semiconductor layer from above the oxide semiconductor layer; an oxide portion formed on the oxide semiconductor layer and at an edge of the first conductive layer, the oxide portion being a oxide of the first conductive layer.
    Type: Application
    Filed: September 29, 2020
    Publication date: April 22, 2021
    Inventors: Tatsuya TODA, Masashi TSUBUKU
  • Patent number: 10964724
    Abstract: The purpose of the present invention is to avoid an inflection point in Vg-Id characteristics of the Thin Film transistor, and to avoid step disconnection of the insulating film formed on the semiconductor layer in the display device. The concrete structure of the present invention is: a display device including a TFT substrate having a thin film transistor (TFT) comprising; the TFT having a channel width and a channel length, a gate insulating film formed on a gate electrode, a semiconductor layer formed on the gate insulating film, wherein the gate electrode, near its edge, has a first sloping surface having a first taper angle in a cross sectional view along the direction of the channel width, an edge of the semiconductor layer in the cross sectional view along the direction of the channel width lies on the first sloping surface of the gate electrode.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 30, 2021
    Assignee: Japan Display Inc.
    Inventor: Tatsuya Toda
  • Publication number: 20210091226
    Abstract: A semiconductor device includes a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor film via the gate insulating film on the gate electrode, a source electrode and a drain electrode on the oxide semiconductor film, a protective film provided on the source electrode and the drain electrode; and a conductive layer provided on the protective film and overlapped on the oxide semiconductor layer. The protective film includes a first silicon oxide film and a first silicon nitride film. The first oxide film is in contact with the oxide semiconductor layer. The gate insulating film includes a second silicon nitride film and a second silicon oxide film. The second silicon oxide film is in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region located between the source electrode and the drain electrode in a plan view.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 25, 2021
    Applicant: Japan Display Inc.
    Inventors: Masashi TSUBUKU, Michiaki SAKAMOTO, Takashi OKADA, Toshiki KANEKO, Tatsuya TODA
  • Publication number: 20210013235
    Abstract: A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Applicant: Japan Display Inc.
    Inventors: Tatsuya TODA, Toshinari SASAKI, Masayoshi FUCHI
  • Publication number: 20190074298
    Abstract: The purpose of the present invention is to avoid an inflection point in Vg-Id characteristics of the Thin Film transistor, and to avoid step disconnection of the insulating film formed on the semiconductor layer in the display device. The concrete structure of the present invention is: a display device including a TFT substrate having a thin film transistor (TFT) comprising; the TFT having a channel width and a channel length, a gate insulating film formed on a gate electrode, a semiconductor layer formed on the gate insulating film, wherein the gate electrode, near its edge, has a first sloping surface having a first taper angle in a cross sectional view along the direction of the channel width, an edge of the semiconductor layer in the cross sectional view along the direction of the channel width lies on the first sloping surface of the gate electrode.
    Type: Application
    Filed: August 22, 2018
    Publication date: March 7, 2019
    Applicant: Japan Display Inc.
    Inventor: Tatsuya TODA