Patents by Inventor Tatsuya Tokue
Tatsuya Tokue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11588475Abstract: A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks.Type: GrantFiled: October 13, 2021Date of Patent: February 21, 2023Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Haruya Iwata, Tatsuya Tokue, Sohei Kushida, Takayuki Mori, Satoshi Kamiya
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Publication number: 20220029612Abstract: A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks.Type: ApplicationFiled: October 13, 2021Publication date: January 27, 2022Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Haruya IWATA, Tatsuya TOKUE, Sohei KUSHIDA, Takayuki MORI, Satoshi KAMIYA
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Patent number: 11177798Abstract: According to one embodiment, there is provided a control method. The method includes controlling a frequency of a clock to a first frequency. The method includes changing the frequency of the clock from the first frequency to a second frequency lower than the first frequency. The method includes statically predicting a time for which the second frequency is to be continued. The method includes changing the frequency of the clock from the second frequency to the first frequency after the time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed to the second frequency.Type: GrantFiled: August 11, 2020Date of Patent: November 16, 2021Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Haruya Iwata, Tatsuya Tokue, Sohei Kushida, Takayuki Mori, Satoshi Kamiya
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Publication number: 20210091756Abstract: According to one embodiment, there is provided a control method. The method includes controlling a frequency of a clock to a first frequency. The method includes changing the frequency of the clock from the first frequency to a second frequency lower than the first frequency. The method includes statically predicting a time for which the second frequency is to be continued. The method includes changing the frequency of the clock from the second frequency to the first frequency after the time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed to the second frequency.Type: ApplicationFiled: August 11, 2020Publication date: March 25, 2021Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Haruya IWATA, Tatsuya TOKUE, Sohei KUSHIDA, Takayuki MORI, Satoshi KAMIYA
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Publication number: 20210089213Abstract: An information processing apparatus comprises a central processor, a volatile memory, a non-volatile memory, a backup line, and a controller. The volatile memory is configured in such a manner that data is input and output thereto and therefrom via a bus under control of the central processor. The non-volatile memory is configured in such a manner that data is input and output thereto and therefrom via the bus under control of the central processor. The backup line is provided between the volatile memory and the non-volatile memory. The controller is configured to control data transfer performed between the volatile memory and the non-volatile memory via the backup line in a transition period between a normal mode of supplying normal power to the volatile memory and a low power consumption mode of reducing or interrupting normal power to be supplied to the volatile memory.Type: ApplicationFiled: March 3, 2020Publication date: March 25, 2021Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Sohei KUSHIDA, Tatsuya TOKUE, Haruya IWATA, Satoshi KAMIYA, Takayuki MORI
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Publication number: 20200301464Abstract: A semiconductor device of an embodiment includes a path monitor circuit provided in a predetermined data path in a circuit that operates with a predetermined source clock, the path monitor circuit being configured to generate an output corresponding to a degree of a timing margin, a power supply voltage control circuit configured to set a power supply voltage that is used in the circuit based on an output of the path monitor circuit, and a clock generating circuit configured to supply to the circuit a clock obtained by dividing a frequency of the source clock, based on a detection result indicating that the power supply voltage obtained based on the output of the path monitor circuit becomes lower than a predetermined threshold.Type: ApplicationFiled: September 5, 2019Publication date: September 24, 2020Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Satoshi KAMIYA, Tatsuya TOKUE
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Patent number: 10775831Abstract: A semiconductor device of an embodiment includes a path monitor circuit provided in a predetermined data path in a circuit that operates with a predetermined source clock, the path monitor circuit being configured to generate an output corresponding to a degree of a timing margin, a power supply voltage control circuit configured to set a power supply voltage that is used in the circuit based on an output of the path monitor circuit, and a clock generating circuit configured to supply to the circuit a clock obtained by dividing a frequency of the source clock, based on a detection result indicating that the power supply voltage obtained based on the output of the path monitor circuit becomes lower than a predetermined threshold.Type: GrantFiled: September 5, 2019Date of Patent: September 15, 2020Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Satoshi Kamiya, Tatsuya Tokue
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Patent number: 10460772Abstract: According to one embodiment, there is provided a semiconductor device comprising: a control circuit connected to a bus; a first circuit operating under control of the control circuit; a bus access detection circuit that detects bus access from the control circuit to the first circuit without going through the bus; a switch element connected between the first circuit and a power supply; and a second circuit connected between the first circuit and the bus, the second circuit controlling, when the bus access to the first circuit is detected by the bus access detection circuit, the switch element such that power from the power supply is supplied to the first circuit.Type: GrantFiled: September 11, 2018Date of Patent: October 29, 2019Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage CorporationInventors: Takayuki Mori, Tatsuya Tokue, Haruya Iwata, Sohei Kushida, Satoshi Kamiya
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Publication number: 20190287577Abstract: According to one embodiment, there is provided a semiconductor device comprising: a control circuit connected to a bus; a first circuit operating under control of the control circuit; a bus access detection circuit that detects bus access from the control circuit to the first circuit without going through the bus; a switch element connected between the first circuit and a power supply; and a second circuit connected between the first circuit and the bus, the second circuit controlling, when the bus access to the first circuit is detected by the bus access detection circuit, the switch element such that power from the power supply is supplied to the first circuit.Type: ApplicationFiled: September 11, 2018Publication date: September 19, 2019Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage CorporationInventors: Takayuki MORI, Tatsuya TOKUE, Haruya IWATA, Sohei KUSHIDA, Satoshi KAMIYA
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Patent number: 8384463Abstract: A clock supply circuit includes a clock generating portion configured to generate a clock signal and to change a frequency of the clock signal from a first frequency to a second frequency being higher than the first frequency; and a intermittent clock generating portion configured to receive the clock signal and to mask a clock pulse of the clock signal at a predetermined rate for a predetermined period when the frequency of the clock signal is changed to the second frequency.Type: GrantFiled: March 29, 2011Date of Patent: February 26, 2013Assignee: Renesas Electronics CorporationInventor: Tatsuya Tokue
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Publication number: 20110248758Abstract: A clock supply circuit includes a clock generating portion configured to generate a clock signal and to change a frequency of the clock signal from a first frequency to a second frequency being higher than the first frequency; and a intermittent clock generating portion configured to receive the clock signal and to mask a clock pulse of the clock signal at a predetermined rate for a predetermined period when the frequency of the clock signal is changed to the second frequency.Type: ApplicationFiled: March 29, 2011Publication date: October 13, 2011Applicant: Renesas Electronics CorporationInventor: Tatsuya TOKUE
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Patent number: 7752467Abstract: The integrated circuit device includes a CPU having an arithmetic circuit and a Power Management Unit implementing power control of the CPU through a power IC. The Power Management Unit has no arithmetic circuit. The Power Management Unit includes RAM storing a plurality of commands and a control section implementing power control of the CPU according to the commands stored in the RAM.Type: GrantFiled: October 4, 2005Date of Patent: July 6, 2010Assignee: Nec Electronics CorporationInventor: Tatsuya Tokue
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Publication number: 20100070793Abstract: Provided is a clock supply device that variably adjusts a frequency of a clock supplied to each module, as needed. The clock supply device includes a clock output unit that switches between clocks having different frequencies and output the clocks; a clock distribution unit that distributes and supplies the clocks from the clock output unit to the plurality of modules; and a clock switching control unit that causes the frequencies of the clocks from the clock output unit to be switched. The clock switching control unit includes a clock request pattern determination unit. The clock request pattern determination unit outputs a control signal for decreasing a clock frequency to a slow frequency, to the clock output unit, when a pattern of a clock request signal output from a monitoring target module satisfies a predetermined condition pattern.Type: ApplicationFiled: September 11, 2009Publication date: March 18, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Tatsuya Tokue
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Publication number: 20060075267Abstract: The integrated circuit device includes a CPU having an arithmetic circuit and a PMU implementing power control of the CPU through a power IC. The PMU has no arithmetic circuit. The PMU includes RAM storing a plurality of commands and a control section implementing power control of the CPU according to the commands stored in the RAM.Type: ApplicationFiled: October 4, 2005Publication date: April 6, 2006Inventor: Tatsuya Tokue