Patents by Inventor Tatsuya Uchino

Tatsuya Uchino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8536905
    Abstract: A level shift circuit including a level shift voltage generation circuit that receives an input signal having an amplitude between a voltage of a first voltage system power supply and a ground potential and performs conversion of the amplitude of the input signal to produce an output signal voltage with an amplitude between a voltage of a second voltage system power supply and the ground potential, a replica circuit monitoring a voltage corresponding to a logic threshold of the first voltage system power supply, the replica circuit, with the logic threshold of the first voltage system power supply as an input, monitoring and outputting a voltage corresponding to a logic threshold of the second voltage system power supply, and a bias generation circuit that receives an output from the replica circuit and generates a bias.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Uchino, Hiromi Saitou
  • Patent number: 8330581
    Abstract: To provide an IC tag, a method of controlling the IC tag, and an IC tag system which can reduce a communication sequence between the reader/writer and the IC tag and can shorten a communication period or a period necessary for executing the command. According to an embodiment of the invention, an IC tag that executes a command processing based on a command received from a redder/writer, includes: a command analyzing unit determining an execution condition of the command received from the redder/writer; and a command execution unit executing a first command processing if the execution condition is met, and executing a second command processing different from the first command processing if the execution condition is not met.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: December 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhiro Akiyama, Hatsuhide Igarashi, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino
  • Patent number: 8264269
    Abstract: A level shift circuit includes a level shift voltage generation circuit that receives an input signal having an amplitude between a first voltage system power supply voltage and a ground potential and outputs an output signal voltage having an amplitude between a second voltage system power supply voltage and the ground potential, a replica circuit configured to be a replica of the level shift voltage generation circuit, the replica circuit monitoring a threshold voltage of a first voltage system and a threshold voltage of a second voltage system, and enabling the level shift voltage generation circuit to generate of the output voltage synchronized in such a manner that, when the input voltage crosses the logic threshold of the first voltage system, the output voltage crosses the logic threshold of the second voltage system, and a bias generation circuit that generates a bias for adjusting variations of the output voltages of the level shift voltage generation circuit and the replica circuit, and supplies the
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: September 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Uchino, Hiromi Saitou
  • Publication number: 20120223760
    Abstract: A level shift circuit including a level shift voltage generation circuit that receives an input signal having an amplitude between a voltage of a first voltage system power supply and a ground potential and performs conversion of the amplitude of the input signal to produce an output signal voltage with an amplitude between a voltage of a second voltage system power supply and the ground potential, a replica circuit monitoring a voltage corresponding to a logic threshold of the first voltage system power supply, the replica circuit, with the logic threshold of the first voltage system power supply as an input, monitoring and outputting a voltage corresponding to a logic threshold of the second voltage system power supply, and a bias generation circuit that receives an output from the replica circuit and generates a bias.
    Type: Application
    Filed: April 11, 2012
    Publication date: September 6, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuya Uchino, Hiromi Saitou
  • Publication number: 20120194321
    Abstract: To provide an IC tag, a method of controlling the IC tag, and an IC tag system which can reduce a communication sequence between the reader/writer and the IC tag and can shorten a communication period or a period necessary for executing the command. According to an embodiment of the invention, an IC tag that executes a command processing based on a command received from a redder/writer, includes: a command analyzing unit determining an execution condition of the command received from the redder/writer; and a command execution unit executing a first command processing if the execution condition is met, and executing a second command processing different from the first command processing if the execution condition is not met.
    Type: Application
    Filed: April 9, 2012
    Publication date: August 2, 2012
    Inventors: Kazuhiro AKIYAMA, Hatsuhide Igarashi, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino
  • Patent number: 8174365
    Abstract: To provide an IC tag, a method of controlling the IC tag, and an IC tag system which can reduce a communication sequence between the reader/writer and the IC tag and can shorten a communication period or a period necessary for executing the command. According to an embodiment of the invention, an IC tag that executes a command processing based on a command received from a redder/writer, includes: a command analyzing unit determining an execution condition of the command received from the redder/writer; and a command execution unit executing a first command processing if the execution condition is met, and executing a second command processing different from the first command processing if the execution condition is not met.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: May 8, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhiro Akiyama, Hatsuhide Igarashi, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino
  • Patent number: 7889055
    Abstract: An IC tag according to an embodiment of the invention includes: a storage circuit having a plurality of memory cells; and a memory control circuit receiving commands by use of a radio signal to control the storage circuit based on the commands, the commands including a specific command to collectively control the plurality of memory cells, and the memory control circuit executing control corresponding to the specific command on the storage circuit based on the specific command and first key data received in association with the specific command.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: February 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhiro Akiyama, Hatsuhide Igarashi, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino
  • Publication number: 20100321084
    Abstract: A level shift circuit includes a level shift voltage generation circuit that receives an input signal having an amplitude between a first voltage system power supply voltage and a ground potential and outputs an output signal voltage having an amplitude between a second voltage system power supply voltage and the ground potential, a replica circuit configured to be a replica of the level shift voltage generation circuit, the replica circuit monitoring a threshold voltage of a first voltage system and a threshold voltage of a second voltage system, and enabling the level shift voltage generation circuit to generate of the output voltage synchronized in such a manner that, when the input voltage crosses the logic threshold of the first voltage system, the output voltage crosses the logic threshold of the second voltage system, and a bias generation circuit that generates a bias for adjusting variations of the output voltages of the level shift voltage generation circuit and the replica circuit, and supplies the
    Type: Application
    Filed: May 28, 2010
    Publication date: December 23, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tatsuya Uchino, Hiromi Saitou
  • Patent number: 7717349
    Abstract: A semiconductor device for an IC tag comprises a receive unit for demodulating receive data from a received RF signal and a signal processing unit for detecting a command comprising data signals from the receive data demodulated by the receive unit and executing processing based on the command, wherein the signal processing unit has a command acceptance mode for detecting the command from the receive data and a command execution mode for executing the command, and cancels the data signal when the data signal is detected from the receive data in the command execution mode.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: May 18, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Kazuhiro Akiyama, Hatsuhide Igarashi, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino, Shigeki Kajimoto
  • Patent number: 7468668
    Abstract: A semiconductor device for an IC tag comprises a receive unit for demodulating receive data from a received RF signal and a signal processing unit for detecting a command comprising data signals from the receive data demodulated by the receive unit and executing processing based on the command, wherein the signal processing unit has a command acceptance mode for detecting the command from the receive data and a command execution mode for executing the command, and generates an error signal when the data signal is not detected from the receive data in the command acceptance mode.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: December 23, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Kazuhiro Akiyama, Hatsuhide Igarashi, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino, Shigeki Kajimoto
  • Publication number: 20070069863
    Abstract: To provide an IC tag, a method of controlling the IC tag, and an IC tag system which can reduce a communication sequence between the reader/writer and the IC tag and can shorten a communication period or a period necessary for executing the command. According to an embodiment of the invention, an IC tag that executes a command processing based on a command received from a redder/writer, includes: a command analyzing unit determining an execution condition of the command received from the redder/writer; and a command execution unit executing a first command processing if the execution condition is met, and executing a second command processing different from the first command processing if the execution condition is not met.
    Type: Application
    Filed: September 26, 2006
    Publication date: March 29, 2007
    Inventors: Kazuhiro Akiyama, Hatsuhide Igarashi, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino
  • Publication number: 20070069860
    Abstract: An IC tag according to an embodiment of the invention includes: a storage circuit having a plurality of memory cells; and a memory control circuit receiving commands by use of a radio signal to control the storage circuit based on the commands, the commands including a specific command to collectively control the plurality of memory cells, and the memory control circuit executing control corresponding to the specific command on the storage circuit based on the specific command and first key data received in association with the specific command.
    Type: Application
    Filed: September 26, 2006
    Publication date: March 29, 2007
    Inventors: Kazuhiro Akiyama, Hatsuhide Igarashi, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino
  • Publication number: 20070069865
    Abstract: According to an embodiment of the invention, an IC tag for receiving a command data including a first command data not requiring the IC tag to send back response data and a second command data requiring the IC tag to send back the response data using a radio signal, including: a control circuit generating a confirmation signal indicating a reception condition of first command data; and a transmitter transmitting the confirmation signal.
    Type: Application
    Filed: September 28, 2006
    Publication date: March 29, 2007
    Inventors: Kazuhiro Akiyama, Hatsuhide Igarashi, Tetsuya Kawasaki, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino, Yuichi Sakurai, Tooru Miura
  • Publication number: 20060022058
    Abstract: A semiconductor device for an IC tag comprises a receive unit for demodulating receive data from a received RF signal and a signal processing unit for detecting a command comprising data signals from the receive data demodulated by the receive unit and executing processing based on the command, wherein the signal processing unit has a command acceptance mode for detecting the command from the receive data and a command execution mode for executing the command, and cancels the data signal when the data signal is detected from the receive data in the command execution mode.
    Type: Application
    Filed: July 28, 2005
    Publication date: February 2, 2006
    Inventors: Kazuhiro Akiyama, Hatsuhide Igarashi, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino, Shigeki Kajimoto
  • Publication number: 20060022803
    Abstract: A semiconductor device, comprises a receive circuit for generating receive data from received radio signals, a power supply voltage generation circuit for generating power supply voltage based on the received radio signals, a control circuit for performing logical processing based on the received data, a transmission circuit for generating radio signals including transmission data and transmitting the radio signals via an antenna and an oscillation circuit, which is operated using the power supply voltage generated by the power supply voltage generation circuit, for generating a predetermined frequency of clocks.
    Type: Application
    Filed: July 28, 2005
    Publication date: February 2, 2006
    Inventors: Kazuhiro Akiyama, Hatsuhide Igarashi, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino, Shigeki Kajimoto
  • Publication number: 20060022798
    Abstract: A communication system comprises an IC tag, and a reader/writer for performing radio communication with the IC tag. The reader/writer further comprises an encoding unit for encoding a digital signal having at least one bit and generating an encoded signal and a transmission unit for transmitting a modulated wave acquired by modulating a carrier based on the encoded signal during an acceptance period when the encoded signal is accepted in the IC tag, and transmitting the carrier to the IC tag during an execution period when the processing based on the encoded signal is executed in the IC tag. The IC tag further comprises a receive unit for receiving the modulated wave or the carrier transmitted from the reader/writer and a power supply voltage generation unit for generating the power supply voltage based on the received modulated wave or the carrier.
    Type: Application
    Filed: July 28, 2005
    Publication date: February 2, 2006
    Inventors: Kazuhiro Akiyama, Hatsuhide Igarashi, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino, Shigeki Kajimoto
  • Publication number: 20060022804
    Abstract: A semiconductor device for an IC tag comprises a receive unit for demodulating receive data from a received RF signal and a signal processing unit for detecting a command comprising data signals from the receive data demodulated by the receive unit and executing processing based on the command, wherein the signal processing unit has a command acceptance mode for detecting the command from the receive data and a command execution mode for executing the command, and generates an error signal when the data signal is not detected from the receive data in the command acceptance mode.
    Type: Application
    Filed: July 28, 2005
    Publication date: February 2, 2006
    Inventors: Kazuhiro Akiyama, Hatsuhide Igarashi, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino, Shigeki Kajimoto