Abstract: A chip resistor includes an insulating substrate, a resistance element, and an electrode. The resistance element includes Cr, Si, and N and is disposed on the insulating substrate. The electrode includes at least one refractory metal and is disposed on the resistance element. An atomic ratio of Si to Cr in the resistance element is greater than or equal to ? and less than or equal to 4 at least at a center of the resistance element in a thickness direction defined with respect to the resistance element. An atom percentage of N in the resistance element is lower than or equal to 50 atom % at least at the center of the resistance element in the thickness direction.

Abstract: A laminated ceramic sintered body board for an electronic device includes a ceramic sintered body board and a flattening film that is provided on an upper surface of the ceramic sintered body board and contains a thermally conductive filler, and the flattening film contains a thermally conductive filler.

Abstract: A laminated ceramic sintered body board for an electronic device includes a ceramic sintered body board and a flattening film that is provided on an upper surface of the ceramic sintered body board and contains a thermally conductive filler, and the flattening film contains a thermally conductive filler.

Abstract: This conductive endless belt can suppress a reduction in toner releasability. The conductive endless belt is used in an image forming apparatus and includes at least an endless base layer and a surface layer formed on an outermost surface of an outer periphery of the base layer. The surface layer is formed from a resin composition including ultraviolet curable resin and silicone resin. The silicone resin includes polysiloxane containing, per molecule, 4 or more of at least one of an acryloyl group and a methacryloyl group.

Abstract: A radar system includes a radar transceiver device, which includes a transmitter front end circuit for transmitting a chirp signal towards an object. The radar transceiver device includes a receiver front end circuit for receiving the reflected chirp signal from the object. The radar transceiver device includes a voltage controlled oscillator (VCO) to generate a transmitted chirp signal. The radar transceiver device includes a mixer configured to generate four intermediate frequency output signals having different phases. The radar system includes a controller device, which includes a processor, and a memory for storing the intermediate frequency output signals and instructions for executing in the processor. The instructions cause the processor to generate a complex Fast Fourier Transform (FFT) result by performing a FFT of the intermediate frequency output signals while using zero-padding.

Abstract: This conductive endless belt can suppress a reduction in toner releasability. The conductive endless belt is used in an image forming apparatus and includes at least an endless base layer and a surface layer formed on an outermost surface of an outer periphery of the base layer. The surface layer is formed from a resin composition including ultraviolet curable resin and silicone resin. The silicone resin includes polysiloxane containing, per molecule, 4 or more of at least one of an acryloyl group and a methacryloyl group.

Abstract: Provided is a logic circuit that can reduce the variation of a power supply voltage supplied thereto and a semiconductor integrated circuit including the logic circuit. The logic circuit includes a buffer unit, a voltage detection unit, and a switch unit. The buffer unit is connected between a first power supply or a voltage regulator and a second power supply to receive power supply, and outputs a signal having the same or inverted logic level as an input signal to an output terminal. The voltage detection unit detects a voltage at the output terminal and outputs a detection signal based on a detection result. The switch unit connects the buffer unit to the first power supply or the voltage regulator in accordance with the detection signal.

Abstract: A down converter has two down converter circuits. The one down converter circuit has a first mixer, a first ½ frequency-divider, and a first PLL. The other down converter circuit has a second mixer, a second ½ frequency-divider, and a second PLL. A difference frequency between a frequency of a local oscillation frequency signal of the second PLL and a frequency of a frequency-divided signal of the first ½ frequency-divider is higher than an upper limit of a receive frequency band of a tuner.

Abstract: A down converter has two down converter circuits. The one down converter circuit has a first mixer, a first ½ frequency-divider, and a first PLL. The other down converter circuit has a second mixer, a second ½ frequency-divider, and a second PLL. A difference frequency between a frequency of a local oscillation frequency signal of the second PLL and a frequency of a frequency-divided signal of the first ½ frequency-divider is higher than an upper limit of a receive frequency band of a tuner.

Abstract: Provided is a logic circuit that can reduce the variation of a power supply voltage supplied thereto and a semiconductor integrated circuit including the logic circuit. The logic circuit includes a buffer unit, a voltage detection unit, and a switch unit. The buffer unit is connected between a first power supply or a voltage regulator and a second power supply to receive power supply, and outputs a signal having the same or inverted logic level as an input signal to an output terminal. The voltage detection unit detects a voltage at the output terminal and outputs a detection signal based on a detection result. The switch unit connects the buffer unit to the first power supply or the voltage regulator in accordance with the detection signal.

Abstract: A receiver includes an automatic gain control (AGC) loop and a filter group that is arranged downstream of the AGC loop. The filter group includes an active filter. The receiver further includes a power difference detector and a switch circuit. The power difference detector detects a power difference between intermediate and output nodes of the filter group to detect presence of an interference wave that is different from a desired wave and that has a frequency near that of the desired wave. The switch circuit switches an operation to suppress a convergence power of the AGC loop when the power difference detector detects the interference wave.

Abstract: The phase locked loop frequency synthesizer, includes: an LC-tank circuit which includes an inductor and a variable capacitor in which the capacity changes depending on the input voltage; a group of fixed-value capacitors which is connected to the LC-tank circuit in parallel; a voltage control oscillating unit which outputs a signal with a frequency determined by the LC-tank circuit and the group of fixed-value capacitors; a phase control unit which generates an output current based on an error operator between a first signal with a divided frequency of a reference frequency and a second signal with a divided frequency of the frequency output from the voltage control oscillating unit; a fixed-value capacitor controlling unit which outputs a selection signal which determines the combination of the fixed-value capacitors to be connected to the LC-tank circuit in parallel based on a frequency dividing ratio setting signal including information about dividing ratio of the second signal, and controls the connectio

Abstract: The phase locked loop frequency synthesizer, includes: an LC-tank circuit which includes an inductor and a variable capacitor in which the capacity changes depending on the input voltage; a group of fixed-value capacitors which is connected to the LC-tank circuit in parallel; a voltage control oscillating unit which outputs a signal with a frequency determined by the LC-tank circuit and the group of fixed-value capacitors; a phase control unit which generates an output current based on an error operator between a first signal with a divided frequency of a reference frequency and a second signal with a divided frequency of the frequency output from the voltage control oscillating unit; a fixed-value capacitor controlling unit which outputs a selection signal which determines the combination of the fixed-value capacitors to be connected to the LC-tank circuit in parallel based on a frequency dividing ratio setting signal including information about dividing ratio of the second signal, and controls the connectio