Patents by Inventor Tatsuya Usami
Tatsuya Usami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240079217Abstract: A wafer placement table includes an upper substrate; a lower substrate; a through hole extending through the lower substrate in an up-down direction; a plurality of projections provided in a dot pattern, for example, at an entirety of an upper surface of the lower substrate and being in contact with the lower surface of the upper substrate; a heat dissipation sheet having a projection insertion hole and being disposed between the upper substrate and the lower substrate; a screw hole provided, in the lower surface of the upper substrate, at a position facing the through hole; a screw member inserted from a lower surface of the lower substrate into the through hole and screwed into the screw hole.Type: ApplicationFiled: February 9, 2023Publication date: March 7, 2024Applicant: NGK Insulators, Ltd.Inventors: Tatsuya KUNO, Taro USAMI, Masaki ISHIKAWA
-
Publication number: 20240079218Abstract: A wafer placement table includes an upper substrate; a lower substrate; a through hole extending through the lower substrate in an up-down direction; a plurality of projections provided in a dot pattern, for example, at an entirety of an upper surface of the lower substrate and being in contact with the lower surface of the upper substrate; a heat dissipation sheet having a projection insertion hole and being disposed between the upper substrate and the lower substrate; a screw hole provided, in the lower surface of the upper substrate, at a position facing the through hole; a screw member inserted from a lower surface of the lower substrate into the through hole and screwed into the screw hole; and a thermally conductive paste interposed, for example, between side surfaces of the projections and an inner peripheral surface of the projection insertion hole of the heat dissipation sheet.Type: ApplicationFiled: February 14, 2023Publication date: March 7, 2024Applicant: NGK Insulators, Ltd.Inventors: Tatsuya KUNO, Taro USAMI, Masaki ISHIKAWA
-
Publication number: 20230411233Abstract: Wirings next to each other spaced apart by a first distance are formed in the uppermost layer of a multilayer wiring layer formed on a semiconductor substrate. A protective film covers upper surfaces and side surfaces of the wirings. The protective films formed on the side surfaces of the wirings are spaced apart from each other. The protective film is formed of an inorganic dielectric film. A thickness of the protective film formed on the upper surfaces of the wirings is larger than a thickness of the protective film formed on the side surfaces of the wirings.Type: ApplicationFiled: April 21, 2023Publication date: December 21, 2023Inventor: Tatsuya USAMI
-
Publication number: 20230103256Abstract: A semiconductor device includes: a semiconductor substrate having first and second main surfaces; interlayer insulating films laminated on the first main surface in a thickness direction from the second main surface toward the first main surface; a top wiring arranged on a top interlayer insulating film of the plurality of interlayer insulating films, which is provided farthest from the first main surface in the thickness direction; and a passivation film arranged on the top interlayer insulating film so as to cover the top wiring. The top wiring includes a first wiring portion and a second wiring portion that extend in a first direction in plan view and are adjacent to each other in a second direction orthogonal to the first direction. A first distance between an upper surface of the top wiring and the top interlayer insulating film in the thickness direction is 2.7 ?m or more.Type: ApplicationFiled: August 22, 2022Publication date: March 30, 2023Inventors: Tatsuya USAMI, Yoshiki MARUYAMA, Yuki MURAYAMA, Yuji ISHII
-
Patent number: 11302596Abstract: A Semiconductor device includes a substrate and a thermal conductive film. The substrate has a top surface and a back surface which oppose with each other. A first opening is formed on the back surface of substrate. The thermal conductive film includes a first thermal conductive portion formed in the first opening. The first thermal conductive portion is embedded in the first opening such that a void is formed in the first opening.Type: GrantFiled: May 13, 2020Date of Patent: April 12, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tatsuya Usami, Hironobu Miyamoto, Masami Sawada
-
Publication number: 20220013481Abstract: A groove is formed between an inner peripheral edge of an opening of a pad electrode and an outer peripheral edge of a bonding region located inside the pad electrode in plan view.Type: ApplicationFiled: July 13, 2020Publication date: January 13, 2022Inventor: Tatsuya USAMI
-
Publication number: 20210184054Abstract: A gallium oxide diode includes: a gallium oxide substrate having an n-type gallium oxide drift layer; an anode electrode of a metal film formed over a front surface of the n-type gallium oxide drift layer; a cathode electrode formed over a rear surface of the gallium oxide substrate; and a reaction layer of a metal oxide film of p-type conductivity formed between the anode electrode and the n-type gallium oxide drift layer. Further, a manufacturing method of a gallium oxide diode includes steps of forming an anode electrode of a metal film over an n-type gallium oxide drift layer formed over a gallium oxide substrate; and forming a reaction layer between the anode electrode and the n-type gallium oxide drift layer by performing a heat treatment to the gallium oxide substrate after forming the anode electrode, the reaction layer being made of a metal oxide film with p-type conductivity.Type: ApplicationFiled: November 18, 2020Publication date: June 17, 2021Inventors: Hironobu MIYAMOTO, Masami SAWADA, Tatsuya USAMI, Tomoo NAKAYAMA
-
Publication number: 20210028082Abstract: A Semiconductor device includes a substrate and a thermal conductive film. The substrate has a top surface and a back surface which oppose with each other. A first opening is formed on the back surface of substrate. The thermal conductive film includes a first thermal conductive portion formed in the first opening. The first thermal conductive portion is embedded in the first opening such that a void is formed in the first opening.Type: ApplicationFiled: May 13, 2020Publication date: January 28, 2021Inventors: Tatsuya USAMI, Hironobu MIYAMOTO, Masami SAWADA
-
Patent number: 10901152Abstract: An SOI substrate is attracted to and detached from an electrostatic chuck included in a semiconductor manufacturing device without failures. A semiconductor device includes a semiconductor substrate made of silicon, a first insulating film formed on a main surface of the semiconductor substrate and configured to generate compression stress to silicon, a waveguide, made of silicon, formed on the first insulating film, and a first interlayer insulating film formed on the first insulating film so as to cover the waveguide. Further, a second insulating film configured to generate tensile stress to silicon is formed on the first interlayer insulating film and in a region distant from the optical waveguide by a thickness of the first insulating film or larger. The second insulating film offsets the compression of the first insulating film.Type: GrantFiled: January 15, 2018Date of Patent: January 26, 2021Assignee: Renesas Electronics CorporationInventor: Tatsuya Usami
-
Patent number: 10734541Abstract: A method of manufacturing the semiconductor device includes: (a) providing a substrate having a semiconductor layer; (b) forming a first insulating film over an insulating layer so as to cover the semiconductor layer; (c) forming an opening extending through the first insulating film and reaching the semiconductor layer; (d) forming, over the semiconductor layer exposed at a bottom surface of the opening, a semiconductor portion having a thickness smaller than that of the first insulating film over the semiconductor layer by a selective epitaxial growth method; (e) forming a second insulating film over the first insulating film and the semiconductor portion; (f) removing the second insulating film from over the first insulating film, while leaving the second insulating film in the opening; (g) removing a semiconductor particle formed over the first insulating film in the (d); and (h) forming a third insulating film over the first insulating film.Type: GrantFiled: August 8, 2018Date of Patent: August 4, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Tatsuya Usami
-
Patent number: 10734336Abstract: Reliability of a semiconductor device is improved. A first pad electrode is formed in an uppermost layer of a multilayer wiring layer, an insulating film of a non-organic material is formed over the first pad electrode, and an organic insulating film is formed over the insulating film. In the organic insulating film, an opening reaching the first pad electrode and a groove reaching the insulating film are formed. Over the organic insulating film, a plurality of re-wirings each having a barrier metal film and a conductive film are formed. In a plan view, the groove is formed in an area between the re-wirings. At the same time, a width of the groove is smaller than a width of a first portion or a width of a second portion of the re-wirings, respectively, neighboring to each other and extending in a first direction.Type: GrantFiled: November 7, 2018Date of Patent: August 4, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Tatsuya Usami
-
Patent number: 10714330Abstract: The reliability of a semiconductor device is improved. A photoresist pattern is formed over a semiconductor substrate. Then, over the semiconductor substrate, a protective film is formed in such a manner as to cover the photoresist pattern. Then, with the photoresist pattern covered with the protective film, an impurity is ion implanted into the semiconductor substrate. Thereafter, the protective film is removed by wet etching, and then, the photoresist pattern is removed.Type: GrantFiled: March 23, 2018Date of Patent: July 14, 2020Assignee: Renesas Electronics CorporationInventors: Tomoo Nakayama, Tatsuya Usami
-
Patent number: 10490517Abstract: A semiconductor device and a manufacturing method thereof according to the present invention include: a first pad electrode formed in an uppermost wiring layer of a multilayer wiring layer; a first insulating film formed on the first pad electrode; and a first organic insulating film formed over the first insulating film. Also, the semiconductor device and the manufacturing method thereof include: a barrier metal film formed on the first organic insulating film and connected to the first pad electrode; and a conductive film formed on the barrier metal film. Then, a second insulating film made of an inorganic material is formed on an upper surface of the first organic insulating film between the barrier metal film and the first organic insulating film.Type: GrantFiled: May 23, 2018Date of Patent: November 26, 2019Assignee: Renesas Electronics CorporationInventor: Tatsuya Usami
-
Patent number: 10401565Abstract: An object of the present invention is to reduce the manufacturing cost of a semiconductor device. A semiconductor device includes a SOI substrate that has an optical waveguide including a semiconductor layer. The optical waveguide is covered with an interlayer insulating film. Wiring parts are formed on the interlayer insulating film. Moreover, a thin film part having a smaller thickness than the wiring parts is formed above the optical waveguide and is integrated with the wiring parts.Type: GrantFiled: May 11, 2018Date of Patent: September 3, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Tatsuya Usami
-
Publication number: 20190237361Abstract: In a semiconductor device, among first wirings, second wirings and a third wiring formed in the same wiring layer, the first wirings having small wiring width are each composed of a stacked film of a first barrier conductor film, a first conductor film made of a material mainly containing a metal element whose mean free path of electrons is smaller than that of copper, and a second barrier conductor film. Also, among the first wirings, the second wirings and the third wiring formed in the same wiring layer, the second wirings and the third wiring having large wiring width are each composed of a stacked film of a third barrier conductor film and a second conductor film made of copper.Type: ApplicationFiled: January 8, 2019Publication date: August 1, 2019Inventor: Tatsuya USAMI
-
Publication number: 20190198468Abstract: Reliability of a semiconductor device is improved. A first pad electrode is formed in an uppermost layer of a multilayer wiring layer, an insulating film of a non-organic material is formed over the first pad electrode, and an organic insulating film is formed over the insulating film. In the organic insulating film, an opening reaching the first pad electrode and a groove reaching the insulating film are formed. Over the organic insulating film, a plurality of re-wirings each having a barrier metal film and a conductive film are formed. In a plan view, the groove is formed in an area between the re-wirings. At the same time, a width of the groove is smaller than a width of a first portion or a width of a second portion of the re-wirings, respectively, neighboring to each other and extending in a first direction.Type: ApplicationFiled: November 7, 2018Publication date: June 27, 2019Inventor: Tatsuya USAMI
-
Patent number: 10295743Abstract: Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region.Type: GrantFiled: August 17, 2015Date of Patent: May 21, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
-
Publication number: 20190123233Abstract: A method of manufacturing the semiconductor device includes: (a) providing a substrate having a semiconductor layer; (b) forming a first insulating film over an insulating layer so as to cover the semiconductor layer; (c) forming an opening extending through the first insulating film and reaching the semiconductor layer; (d) forming, over the semiconductor layer exposed at a bottom surface of the opening, a semiconductor portion having a thickness smaller than that of the first insulating film over the semiconductor layer by a selective epitaxial growth method; (e) forming a second insulating film over the first insulating film and the semiconductor portion; (f) removing the second insulating film from over the first insulating film, while leaving the second insulating film in the opening; (g) removing a semiconductor particle formed over the first insulating film in the (d); and (h) forming a third insulating film over the first insulating film.Type: ApplicationFiled: August 8, 2018Publication date: April 25, 2019Inventor: Tatsuya USAMI
-
Patent number: 10256133Abstract: To improve the characteristics of a semiconductor device having a substrate contact formed in a deep trench. In a method of forming a plug PSUB in a deep trench DT2 that penetrates an n-type buried layer NBL and reaches a p-type epitaxial layer PEP1, the plug PSUB is formed in the deep trench DT2 after a metal silicide layer SIL1 is formed in the p-type epitaxial layer PEP1. The metal silicide layer SIL1 is formed using a PVD-first metal film (a first metal film formed by PVD). A first barrier metal film BM1 at the bottom of the plug PSUB is a CVD-second metal film (a second metal film formed by CVD). The first metal film is a metal film different from the second metal film.Type: GrantFiled: October 26, 2017Date of Patent: April 9, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Tatsuya Usami
-
Patent number: 10256135Abstract: To provide a semiconductor device having a substrate contact in a deep trench thereof and having an improved characteristic. A PVD-metal film (metal film formed by PVD) is used as a first barrier metal film which is a lowermost layer barrier metal film formed in a deep trench penetrating an n type epitaxial layer and a reaching a layer therebelow. Such a configuration makes it possible to stably form a metal silicide layer at a boundary between the PVD-metal film and a silicon layer therebelow (or silicon substrate) and thereby stabilize the contact resistance.Type: GrantFiled: October 17, 2017Date of Patent: April 9, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Tatsuya Usami