Patents by Inventor Tatsuya YANAGI
Tatsuya YANAGI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11933836Abstract: For example, a method of measuring a device parameter includes: a step of repeatedly measuring the gate-source voltage (or gate-emitter voltage) of a switching element in its switching transient state while switching the external gate resistance for the switching element among m resistance values (where m is an integer of three or more); and a step of, while representing the internal gate resistance and the plateau voltage of the switching element by Rgin and Vp respectively and using the m resistance values of the external gate resistance and corresponding m voltage values of the gate-source voltage (or gate-emitter voltage) as Rg(k) and Vgs(k) respectively (where k=1, 2 . . . m), performing the fitting of the equation Vgs(k)=Rg(k)/(Rg(k)+Rgin)×Vp, thereby to derive the internal gate resistance Rgin or the plateau voltage Vp of the switching element.Type: GrantFiled: March 27, 2020Date of Patent: March 19, 2024Assignee: Rohm Co., Ltd.Inventor: Tatsuya Yanagi
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Publication number: 20220216795Abstract: A power conversion circuit in which a switching transistor and a synchronous rectifier transistor are connected in series, and a source inductance of the switching transistor is smaller than a source inductance of the synchronous rectifier transistor.Type: ApplicationFiled: March 25, 2022Publication date: July 7, 2022Inventors: Tatsuya YANAGI, Hirotaka OTAKE
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Publication number: 20220146566Abstract: For example, a method of measuring a device parameter includes: a step of repeatedly measuring the gate-source voltage (or gate-emitter voltage) of a switching element in its switching transient state while switching the external gate resistance for the switching element among m resistance values (where m is an integer of three or more); and a step of, while representing the internal gate resistance and the plateau voltage of the switching element by Rgin and Vp respectively and using the m resistance values of the external gate resistance and corresponding m voltage values of the gate-source voltage (or gate-emitter voltage) as Rg(k) and Vgs(k) respectively (where k=1, 2 . . . m), performing the fitting of the equation Vgs(k)=Rg(k)/(Rg(k)+Rgin)×Vp, thereby to derive the internal gate resistance Rgin or the plateau voltage Vp of the switching element.Type: ApplicationFiled: March 27, 2020Publication date: May 12, 2022Inventor: Tatsuya YANAGI
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Patent number: 11175332Abstract: A method for measuring current-voltage characteristics representing the relationship between the drain current and the drain-source voltage of a first transistor includes: a first step of setting the drain current and the drain-source voltage using a voltage source and a current source connected in series with the first transistor and a rectifying element connected in parallel with, with the reverse polarity to, an inductive load as the current source; a second step of measuring the gate-source voltage and the gate current in the switching transient state of the first transistor; and a third step of calculating the voltage applied to the gate oxide film of the first transistor using the results of the measurement of the gate-source voltage and the gate current and acquiring the current-voltage characteristics of the first transistor using the result of the calculation.Type: GrantFiled: January 16, 2019Date of Patent: November 16, 2021Assignee: Rohm Co., Ltd.Inventors: Yohei Nakamura, Tatsuya Yanagi
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Publication number: 20210132136Abstract: A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.Type: ApplicationFiled: December 31, 2020Publication date: May 6, 2021Inventors: Tatsuya YANAGI, Hirotaka OTAKE, Hiroyuki SAKAIRI, Naotaka KURODA
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Publication number: 20210063469Abstract: A method for measuring current-voltage characteristics representing the relationship between the drain current and the drain-source voltage of a first transistor includes: a first step of setting the drain current and the drain-source voltage using a voltage source and a current source connected in series with the first transistor and a rectifying element connected in parallel with, with the reverse polarity to, an inductive load as the current source; a second step of measuring the gate-source voltage and the gate current in the switching transient state of the first transistor; and a third step of calculating the voltage applied to the gate oxide film of the first transistor using the results of the measurement of the gate-source voltage and the gate current and acquiring the current-voltage characteristics of the first transistor using the result of the calculation.Type: ApplicationFiled: January 16, 2019Publication date: March 4, 2021Applicant: Rohm Co., Ltd.Inventors: Yohei NAKAMURA, Tatsuya YANAGI
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Patent number: 10917080Abstract: A gate drive circuit has a capacitor and a gate drive voltage source connected in series with a gate terminal of a voltage-driven switching device. The gate drive source voltage feeds, as a gate drive voltage, a voltage higher than the sum of the voltage applied to a gate-source parasitic capacitance of the switching device when the switching device is in a steady ON state and the voltage applied to, of any circuit component interposed between the gate drive voltage source and the gate terminal of the switching device, a circuit component other than the capacitor (such as an upper transistor forming the output stage of the driver). No other circuit component (such as a resistor connected in parallel with the capacitor) is essential but the capacitor as the sole circuit component to be directly connected to the gate terminal of the switching device.Type: GrantFiled: March 30, 2017Date of Patent: February 9, 2021Assignee: Rohm Co., Ltd.Inventors: Tatsuya Yanagi, Hirotaka Otake, Takashi Sawada, Seiya Kitagawa
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Patent number: 10908204Abstract: A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.Type: GrantFiled: March 29, 2017Date of Patent: February 2, 2021Assignee: Rohm Co., Ltd.Inventors: Tatsuya Yanagi, Hirotaka Otake, Hiroyuki Sakairi, Naotaka Kuroda
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Patent number: 10901024Abstract: A method for measuring a current-voltage characteristic (Id?Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id?Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.Type: GrantFiled: February 27, 2018Date of Patent: January 26, 2021Assignee: Rohm Co., Ltd.Inventors: Tatsuya Yanagi, Hirotaka Otake, Hiroyuki Sakairi, Naotaka Kuroda
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Patent number: 10749520Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.Type: GrantFiled: April 24, 2019Date of Patent: August 18, 2020Assignee: ROHM CO., LTD.Inventors: Hirotaka Otake, Tatsuya Yanagi, Yusuke Nakakohara
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Publication number: 20190253047Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.Type: ApplicationFiled: April 24, 2019Publication date: August 15, 2019Inventors: Hirotaka OTAKE, Tatsuya YANAGI, Yusuke NAKAKOHARA
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Patent number: 10320380Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.Type: GrantFiled: October 4, 2017Date of Patent: June 11, 2019Assignee: ROHM CO., LTD.Inventors: Hirotaka Otake, Tatsuya Yanagi, Yusuke Nakakohara
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Publication number: 20180188312Abstract: A method for measuring a current-voltage characteristic (Id?Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id?Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Inventors: Tatsuya YANAGI, Hirotaka OTAKE, Hiroyuki SAKAIRI, Naotaka KURODA
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Publication number: 20180048306Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.Type: ApplicationFiled: October 4, 2017Publication date: February 15, 2018Inventors: Hirotaka OTAKE, Tatsuya YANAGI, Yusuke NAKAKOHARA
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Patent number: 9819338Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.Type: GrantFiled: June 24, 2016Date of Patent: November 14, 2017Assignee: ROHM CO., LTD.Inventors: Hirotaka Otake, Tatsuya Yanagi, Yusuke Nakakohara
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Publication number: 20170285095Abstract: A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.Type: ApplicationFiled: March 29, 2017Publication date: October 5, 2017Inventors: Tatsuya YANAGI, Hirotaka OTAKE, Hiroyuki SAKAIRI, Naotaka KURODA
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Publication number: 20170288657Abstract: A gate drive circuit has a capacitor and a gate drive voltage source connected in series with a gate terminal of a voltage-driven switching device. The gate drive source voltage feeds, as a gate drive voltage, a voltage higher than the sum of the voltage applied to a gate-source parasitic capacitance of the switching device when the switching device is in a steady ON state and the voltage applied to, of any circuit component interposed between the gate drive voltage source and the gate terminal of the switching device, a circuit component other than the capacitor (such as an upper transistor forming the output stage of the driver). No other circuit component (such as a resistor connected in parallel with the capacitor) is essential but the capacitor as the sole circuit component to be directly connected to the gate terminal of the switching device.Type: ApplicationFiled: March 30, 2017Publication date: October 5, 2017Inventors: Tatsuya YANAGI, Hirotaka OTAKE, Takashi SAWADA, Seiya KITAGAWA
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Publication number: 20160308523Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate. There can be provided the power circuit capable of reducing the misoperation and the parasitic oscillation and capable of realizing the high speed switching performance.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Inventors: Hirotaka OTAKE, Tatsuya YANAGI, Yusuke NAKAKOHARA