Patents by Inventor Tatsuya YANAGI

Tatsuya YANAGI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11933836
    Abstract: For example, a method of measuring a device parameter includes: a step of repeatedly measuring the gate-source voltage (or gate-emitter voltage) of a switching element in its switching transient state while switching the external gate resistance for the switching element among m resistance values (where m is an integer of three or more); and a step of, while representing the internal gate resistance and the plateau voltage of the switching element by Rgin and Vp respectively and using the m resistance values of the external gate resistance and corresponding m voltage values of the gate-source voltage (or gate-emitter voltage) as Rg(k) and Vgs(k) respectively (where k=1, 2 . . . m), performing the fitting of the equation Vgs(k)=Rg(k)/(Rg(k)+Rgin)×Vp, thereby to derive the internal gate resistance Rgin or the plateau voltage Vp of the switching element.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: March 19, 2024
    Assignee: Rohm Co., Ltd.
    Inventor: Tatsuya Yanagi
  • Publication number: 20220216795
    Abstract: A power conversion circuit in which a switching transistor and a synchronous rectifier transistor are connected in series, and a source inductance of the switching transistor is smaller than a source inductance of the synchronous rectifier transistor.
    Type: Application
    Filed: March 25, 2022
    Publication date: July 7, 2022
    Inventors: Tatsuya YANAGI, Hirotaka OTAKE
  • Publication number: 20220146566
    Abstract: For example, a method of measuring a device parameter includes: a step of repeatedly measuring the gate-source voltage (or gate-emitter voltage) of a switching element in its switching transient state while switching the external gate resistance for the switching element among m resistance values (where m is an integer of three or more); and a step of, while representing the internal gate resistance and the plateau voltage of the switching element by Rgin and Vp respectively and using the m resistance values of the external gate resistance and corresponding m voltage values of the gate-source voltage (or gate-emitter voltage) as Rg(k) and Vgs(k) respectively (where k=1, 2 . . . m), performing the fitting of the equation Vgs(k)=Rg(k)/(Rg(k)+Rgin)×Vp, thereby to derive the internal gate resistance Rgin or the plateau voltage Vp of the switching element.
    Type: Application
    Filed: March 27, 2020
    Publication date: May 12, 2022
    Inventor: Tatsuya YANAGI
  • Patent number: 11175332
    Abstract: A method for measuring current-voltage characteristics representing the relationship between the drain current and the drain-source voltage of a first transistor includes: a first step of setting the drain current and the drain-source voltage using a voltage source and a current source connected in series with the first transistor and a rectifying element connected in parallel with, with the reverse polarity to, an inductive load as the current source; a second step of measuring the gate-source voltage and the gate current in the switching transient state of the first transistor; and a third step of calculating the voltage applied to the gate oxide film of the first transistor using the results of the measurement of the gate-source voltage and the gate current and acquiring the current-voltage characteristics of the first transistor using the result of the calculation.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: November 16, 2021
    Assignee: Rohm Co., Ltd.
    Inventors: Yohei Nakamura, Tatsuya Yanagi
  • Publication number: 20210132136
    Abstract: A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.
    Type: Application
    Filed: December 31, 2020
    Publication date: May 6, 2021
    Inventors: Tatsuya YANAGI, Hirotaka OTAKE, Hiroyuki SAKAIRI, Naotaka KURODA
  • Publication number: 20210063469
    Abstract: A method for measuring current-voltage characteristics representing the relationship between the drain current and the drain-source voltage of a first transistor includes: a first step of setting the drain current and the drain-source voltage using a voltage source and a current source connected in series with the first transistor and a rectifying element connected in parallel with, with the reverse polarity to, an inductive load as the current source; a second step of measuring the gate-source voltage and the gate current in the switching transient state of the first transistor; and a third step of calculating the voltage applied to the gate oxide film of the first transistor using the results of the measurement of the gate-source voltage and the gate current and acquiring the current-voltage characteristics of the first transistor using the result of the calculation.
    Type: Application
    Filed: January 16, 2019
    Publication date: March 4, 2021
    Applicant: Rohm Co., Ltd.
    Inventors: Yohei NAKAMURA, Tatsuya YANAGI
  • Patent number: 10917080
    Abstract: A gate drive circuit has a capacitor and a gate drive voltage source connected in series with a gate terminal of a voltage-driven switching device. The gate drive source voltage feeds, as a gate drive voltage, a voltage higher than the sum of the voltage applied to a gate-source parasitic capacitance of the switching device when the switching device is in a steady ON state and the voltage applied to, of any circuit component interposed between the gate drive voltage source and the gate terminal of the switching device, a circuit component other than the capacitor (such as an upper transistor forming the output stage of the driver). No other circuit component (such as a resistor connected in parallel with the capacitor) is essential but the capacitor as the sole circuit component to be directly connected to the gate terminal of the switching device.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: February 9, 2021
    Assignee: Rohm Co., Ltd.
    Inventors: Tatsuya Yanagi, Hirotaka Otake, Takashi Sawada, Seiya Kitagawa
  • Patent number: 10908204
    Abstract: A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: February 2, 2021
    Assignee: Rohm Co., Ltd.
    Inventors: Tatsuya Yanagi, Hirotaka Otake, Hiroyuki Sakairi, Naotaka Kuroda
  • Patent number: 10901024
    Abstract: A method for measuring a current-voltage characteristic (Id?Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id?Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: January 26, 2021
    Assignee: Rohm Co., Ltd.
    Inventors: Tatsuya Yanagi, Hirotaka Otake, Hiroyuki Sakairi, Naotaka Kuroda
  • Patent number: 10749520
    Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: August 18, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Hirotaka Otake, Tatsuya Yanagi, Yusuke Nakakohara
  • Publication number: 20190253047
    Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.
    Type: Application
    Filed: April 24, 2019
    Publication date: August 15, 2019
    Inventors: Hirotaka OTAKE, Tatsuya YANAGI, Yusuke NAKAKOHARA
  • Patent number: 10320380
    Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: June 11, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Hirotaka Otake, Tatsuya Yanagi, Yusuke Nakakohara
  • Publication number: 20180188312
    Abstract: A method for measuring a current-voltage characteristic (Id?Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id?Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.
    Type: Application
    Filed: February 27, 2018
    Publication date: July 5, 2018
    Inventors: Tatsuya YANAGI, Hirotaka OTAKE, Hiroyuki SAKAIRI, Naotaka KURODA
  • Publication number: 20180048306
    Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.
    Type: Application
    Filed: October 4, 2017
    Publication date: February 15, 2018
    Inventors: Hirotaka OTAKE, Tatsuya YANAGI, Yusuke NAKAKOHARA
  • Patent number: 9819338
    Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: November 14, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Hirotaka Otake, Tatsuya Yanagi, Yusuke Nakakohara
  • Publication number: 20170285095
    Abstract: A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 5, 2017
    Inventors: Tatsuya YANAGI, Hirotaka OTAKE, Hiroyuki SAKAIRI, Naotaka KURODA
  • Publication number: 20170288657
    Abstract: A gate drive circuit has a capacitor and a gate drive voltage source connected in series with a gate terminal of a voltage-driven switching device. The gate drive source voltage feeds, as a gate drive voltage, a voltage higher than the sum of the voltage applied to a gate-source parasitic capacitance of the switching device when the switching device is in a steady ON state and the voltage applied to, of any circuit component interposed between the gate drive voltage source and the gate terminal of the switching device, a circuit component other than the capacitor (such as an upper transistor forming the output stage of the driver). No other circuit component (such as a resistor connected in parallel with the capacitor) is essential but the capacitor as the sole circuit component to be directly connected to the gate terminal of the switching device.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 5, 2017
    Inventors: Tatsuya YANAGI, Hirotaka OTAKE, Takashi SAWADA, Seiya KITAGAWA
  • Publication number: 20160308523
    Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate. There can be provided the power circuit capable of reducing the misoperation and the parasitic oscillation and capable of realizing the high speed switching performance.
    Type: Application
    Filed: June 24, 2016
    Publication date: October 20, 2016
    Inventors: Hirotaka OTAKE, Tatsuya YANAGI, Yusuke NAKAKOHARA