Patents by Inventor Tatsuyuki Okubo

Tatsuyuki Okubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230120615
    Abstract: A semiconductor manufacturing apparatus includes a thrust-up unit having a plurality of blocks in contact with a dicing tape, a head having a collet absorbing the die and capable of being moved up and down, and a control section controlling the operation of the thrust-up unit and the head. The thrust-up unit can operate each of the plurality of blocks independently. The control section configures the thrust-up sequences of the plurality of blocks in a plurality of steps, and controls the operation of the plurality of blocks on the basis of a time chart recipe capable of setting the height and the speed of the plurality of blocks for each block and in each step.
    Type: Application
    Filed: December 16, 2022
    Publication date: April 20, 2023
    Inventors: Tsuyoshi YOKOMORI, Tatsuyuki OKUBO, Yuki NAKUI, Hiroshi MAKI, Akira SAITO, Naoki OKAMOTO
  • Patent number: 11569118
    Abstract: A semiconductor manufacturing apparatus includes a thrust-up unit having a plurality of blocks in contact with a dicing tape, a head having a collet absorbing the die and capable of being moved up and down, and a control section controlling the operation of the thrust-up unit and the head. The thrust-up unit can operate each of the plurality of blocks independently. The control section configures the thrust-up sequences of the plurality of blocks in a plurality of steps, and controls the operation of the plurality of blocks on the basis of a time chart recipe capable of setting the height and the speed of the plurality of blocks for each block and in each step.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: January 31, 2023
    Assignee: Fasford Technology Co., Ltd.
    Inventors: Tsuyoshi Yokomori, Tatsuyuki Okubo, Yuki Nakui, Hiroshi Maki, Akira Saito, Naoki Okamoto
  • Publication number: 20200312699
    Abstract: A semiconductor manufacturing apparatus includes a thrust-up unit having a plurality of blocks in contact with a dicing tape, a head having a collet absorbing the die and capable of being moved up and down, and a control section controlling the operation of the thrust-up unit and the head. The thrust-up unit can operate each of the plurality of blocks independently. The control section configures the thrust-up sequences of the plurality of blocks in a plurality of steps, and controls the operation of the plurality of blocks on the basis of a time chart recipe capable of setting the height and the speed of the plurality of blocks for each block and in each step.
    Type: Application
    Filed: March 9, 2020
    Publication date: October 1, 2020
    Inventors: Tsuyoshi YOKOMORI, Tatsuyuki OKUBO, Yuki NAKUI, Hiroshi MAKI, Akira SAITO, Naoki OKAMOTO
  • Patent number: 8703583
    Abstract: A technique with which die bonding can be carried out without forming a void in a bond area is provided. A vacuum supply line that connects to a vacuum chuck hole formed in the bottom face of a vacuuming collet and supplies the vacuuming collet with reduced pressure for vacuum chucking a chip is constructed of two systems. That is, the vacuum supply line is so structured that a first pipe and a second pipe connect to the vacuuming collet. The first pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is unstuck from a dicing tape and transported to a mounting position on a wiring substrate. The second pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is mounted over a wiring substrate. The intensity of the vacuum (suction force) supplied to the vacuuming collet is controlled by opening or closing valves respectively installed in the pipes.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: April 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Maki, Masayuki Mochizuki, Ryuichi Takano, Yoshiaki Makita, Haruhiko Fukasawa, Keisuke Nadamoto, Tatsuyuki Okubo
  • Publication number: 20130299098
    Abstract: In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.
    Type: Application
    Filed: July 14, 2013
    Publication date: November 14, 2013
    Inventors: Hiroshi MAKI, Tsuyoshi YOKOMORI, Tatsuyuki OKUBO
  • Publication number: 20130276989
    Abstract: A paste applying apparatus and method apply a paste within an application area. A drawing pattern is determined in advance, within the application area, for each of the application areas, and the drawing pattern has, at least, a first drawing route and a fifth drawing route for drawing in horizontal direction, a second drawing route and a fourth drawing route for drawing obliquely, and further a third drawing route, in vicinity of a side of the application area in the horizontal direction. A controller portion controls the discharge portion and the moving portion, so that the paste is applied, continuously, from a drawing start-point to a drawing end-point, which are determined in advance, through the first drawing route, the second drawing route, the third drawing route, the fourth drawing route and the fifth drawing route.
    Type: Application
    Filed: August 16, 2012
    Publication date: October 24, 2013
    Inventors: Tatsuyuki OKUBO, Mitsuo Yoda, Shigeru Otake
  • Patent number: 8492173
    Abstract: In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: July 23, 2013
    Assignee: Renesas Electonics Corporation
    Inventors: Hiroshi Maki, Tsuyoshi Yokomori, Tatsuyuki Okubo
  • Patent number: 8460491
    Abstract: The present invention provides die bonder and bonding method by which a bonding load from a high load to a low load is obtained or high-speed mounting is attained. In a die bonder or a bonding method in which a bonding head is ascended/descended by a first ascending/descending drive shaft unit, a die is picked up, the picked-up die is installed onto a workpiece, and after installed, a load is exerted on the die by the bonding head to bond the die to the workpiece, whether the load is higher/lower than a predetermined load is determined, and in bonding, when the load is higher than the predetermined load, the high load is exerted by the first ascending/descending drive shaft unit, and when the load is lower than the predetermined load, the low load is exerted by a second ascending/descending drive shaft unit.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: June 11, 2013
    Assignee: Hitachi High-Tech Instruments Co., Ltd.
    Inventors: Shingo Fukasawa, Tatsuyuki Okubo, Yoshihiro Kurihara
  • Patent number: 8372665
    Abstract: In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: February 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Maki, Tsuyoshi Yokomori, Tatsuyuki Okubo
  • Publication number: 20120270340
    Abstract: In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.
    Type: Application
    Filed: June 26, 2012
    Publication date: October 25, 2012
    Inventors: HIROSHI MAKI, Tsuyoshi Yokomori, Tatsuyuki Okubo
  • Patent number: 8222050
    Abstract: In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Maki, Tsuyoshi Yokomori, Tatsuyuki Okubo
  • Publication number: 20110290427
    Abstract: In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.
    Type: Application
    Filed: August 11, 2011
    Publication date: December 1, 2011
    Inventors: Hiroshi Maki, Tsuyoshi Yokomori, Tatsuyuki Okubo
  • Patent number: 8003495
    Abstract: In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: August 23, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Maki, Tsuyoshi Yokomori, Tatsuyuki Okubo
  • Publication number: 20110097849
    Abstract: In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.
    Type: Application
    Filed: January 10, 2011
    Publication date: April 28, 2011
    Inventors: Hiroshi Maki, Tsuyoshi Yokomori, Tatsuyuki Okubo
  • Patent number: 7888141
    Abstract: In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: February 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Maki, Tsuyoshi Yokomori, Tatsuyuki Okubo
  • Publication number: 20100055878
    Abstract: A technique with which die bonding can be carried out without forming a void in a bond area is provided. A vacuum supply line that connects to a vacuum chuck hole formed in the bottom face of a vacuuming collet and supplies the vacuuming collet with reduced pressure for vacuum chucking a chip is constructed of two systems. That is, the vacuum supply line is so structured that a first pipe and a second pipe connect to the vacuuming collet. The first pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is unstuck from a dicing tape and transported to a mounting position on a wiring substrate. The second pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is mounted over a wiring substrate. The intensity of the vacuum (suction force) supplied to the vacuuming collet is controlled by opening or closing valves respectively installed in the pipes.
    Type: Application
    Filed: November 13, 2009
    Publication date: March 4, 2010
    Inventors: Hiroshi MAKI, Masayuki Mochizuki, Ryuichi Takano, Yoshiaki Makita, Haruhiko Fukasawa, Keisuke Nadamoto, Tatsuyuki Okubo
  • Patent number: 7629231
    Abstract: A technique with which die bonding can be carried out without forming a void in a bond area is provided. A vacuum supply line that connects to a vacuum chuck hole formed in the bottom face of a vacuuming collet and supplies the vacuuming collet with reduced pressure for vacuum chucking a chip is constructed of two systems. That is, the vacuum supply line is so structured that a first pipe and a second pipe connect to the vacuuming collet. The first pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is unstuck from a dicing tape and transported to a mounting position on a wiring substrate. The second pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is mounted over a wiring substrate. The intensity of the vacuum (suction force) supplied to the vacuuming collet is controlled by opening or closing valves respectively installed in the pipes.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: December 8, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Maki, Masayuki Mochizuki, Ryuichi Takano, Yoshiaki Makita, Haruhiko Fukasawa, Keisuke Nadamoto, Tatsuyuki Okubo
  • Publication number: 20080318346
    Abstract: In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 25, 2008
    Inventors: Hiroshi Maki, Tsuyoshi Yokomori, Tatsuyuki Okubo
  • Publication number: 20070275544
    Abstract: A technique with which die bonding can be carried out without forming a void in a bond area is provided. A vacuum supply line that connects to a vacuum chuck hole formed in the bottom face of a vacuuming collet and supplies the vacuuming collet with reduced pressure for vacuum chucking a chip is constructed of two systems. That is, the vacuum supply line is so structured that a first pipe and a second pipe connect to the vacuuming collet. The first pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is unstuck from a dicing tape and transported to a mounting position on a wiring substrate. The second pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is mounted over a wiring substrate. The intensity of the vacuum (suction force) supplied to the vacuuming collet is controlled by opening or closing valves respectively installed in the pipes.
    Type: Application
    Filed: April 16, 2007
    Publication date: November 29, 2007
    Inventors: Hiroshi Maki, Masayuki Mochizuki, Ryuichi Takano, Yoshiaki Makita, Haruhiko Fukasawa, Keisuke Nadamoto, Tatsuyuki Okubo