Patents by Inventor Taturou Yamashita

Taturou Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6347037
    Abstract: A semiconductor device includes a board and a semiconductor chip which is connected to an upper surface of the board via face-down bonding. The semiconductor device further includes a frame-shape member which is connected to the upper surface of the board with first adhesive, and has an opening to accommodate the semiconductor chip therein, and a plate-shape member which is situated to cover the semiconductor chip and the frame-shape member, and is connected to the semiconductor chip and the frame-shape member with second adhesive, wherein the frame-shape member has such a sufficient sturdiness as to prevent thermal-expansion-induced deformations of the board and the plate-shape member.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: February 12, 2002
    Assignee: Fujitsu Limited
    Inventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi, Masaru Nukiwa, Takao Akai
  • Publication number: 20020001178
    Abstract: A semiconductor device includes a board and a semiconductor chip which is connected to an upper surface of the board via face-down bonding. The semiconductor device further includes a frame-shape member which is connected to the upper surface of the board with first adhesive, and has an opening to accommodate the semiconductor chip therein, and a plate-shape member which is situated to cover the semiconductor chip and the frame-shape member, and is connected to the semiconductor chip and the frame-shape member with second adhesive, wherein the frame-shape member has such a sufficient sturdiness as to prevent thermal-expansion-induced deformations of the board and the plate-shape member.
    Type: Application
    Filed: November 4, 1998
    Publication date: January 3, 2002
    Inventors: MAKOTO IIJIMA, TETSUSHI WAKABAYASHI, TOSHIO HAMANO, MASAHARU MINAMIZAWA, MASASHI TAKENAKA, TATUROU YAMASHITA, MASATAKA MIZUKOSHI, MASARU NUKIWA, TAKAO AKAI
  • Patent number: 6184133
    Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi
  • Patent number: 6088233
    Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: July 11, 2000
    Assignee: Fujitsu Limited
    Inventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi
  • Patent number: 5978222
    Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: November 2, 1999
    Assignee: Fujitsu Limited
    Inventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi
  • Patent number: 5889333
    Abstract: A semiconductor device includes a device body including at least an LSI chip, and a lead structure having a base which is flexible and a plurality of pins which project from both sides of the base. The lead structure is integrated with the device body so that first ends of the plurality of pins are electrically connected to the LSI chip. The semiconductor device is manufactured in accordance with two steps of forming the lead structure and of integrating the lead structure with the deice body so that the first ends of the plurality of pins are electrically connected to the LSI chip.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: March 30, 1999
    Assignee: Fujitsu Limited
    Inventors: Masashi Takenaka, Junichi Kasai, Masataka Mizukoshi, Taturou Yamashita
  • Patent number: 5729435
    Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, and an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths. The semiconductor device further includes a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a passage restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: March 17, 1998
    Assignee: Fujitsu Limited
    Inventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi
  • Patent number: 5726493
    Abstract: A semiconductor device or a semiconductor device unit having a ball-grid-array type package structure, comprises a semiconductor element, a base having a mounting surface and a connection surface opposite to each other, the semiconductor element being mounted on the mounting surface, a plurality of balls which function as external connection terminals being provided on the connection surface, a sealing resin sealing the semiconductor element, and an electrically conductive electrode member, a first end of the electrode member being electrically connected to the semiconductor element on the mounting surface of the base, a second end of the electrode member being electrically connective to an outer terminal. An electrically conductive pin which can pass through the sealing resin can be used as the electrode member. Even after the semiconductor device is mounted on a circuit board, a test on the semiconductor element can be conducted.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: March 10, 1998
    Assignee: Fujitsu Limited
    Inventors: Taturou Yamashita, Masashi Takenaka