Patents by Inventor Tatyania Andryushchenko

Tatyania Andryushchenko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150270211
    Abstract: Interconnect structures including a selective via post disposed on a top surface of a lower level interconnect feature, and fabrication techniques to selectively form such a post. Following embodiments herein, a minimum interconnect line spacing may be maintained independent of registration error in a via opening. In embodiments, a selective via post has a bottom lateral dimension smaller than that of a via opening within which the post is disposed. Formation of a conductive via post may be preferential to a top surface of the lower interconnect feature exposed by the via opening. A subsequently deposited dielectric material backfills portions of a via opening extending beyond the interconnect feature where no conductive via post was formed. An upper level interconnect feature is landed on the selective via post to electrically interconnect with the lower level feature.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 24, 2015
    Inventors: Mauro Kobrinsky, Tatyania Andryushchenko, Ramanan Chebiam, Hui Jae Yoo