Abstract: An emulation system includes a first platform device, a second platform device, and a processing device. The first platform device includes first integrated circuit (IC) devices. The first IC devices emulate a circuit design for verification of the circuit design. The second platform device includes second IC devices. The processing device connected to the first platform device and the second platform device. The processing device configured to emulate the circuit design using one or more of the second IC devices based on a failure associated with the first platform device being detected.

Abstract: Low-latency gigabit transceiver PHY-based signal switching for emulation, prototyping, and high performance computing (HPC) in a computing platform that includes multiple ICs, where a first one of the ICs includes functional circuitry, a receiver that receives a signal from a second one of the ICs, a transmitter that transmits outgoing data to a third one of the ICs, and a bypass circuit that provides an output of the receiver to one of the functional circuitry and the transmitter (e.g., based on a destination address). The bypass circuit may bypass the functional circuitry, and may further bypass a receive-side media access controller (MAC) and a transmit-side MAC. The IC may multiplex outgoing data to the transmitters. Selectable functions of PHY circuitry may be disabled in bypass mode. The ICs may include field-programmable gate arrays, which may be programmed to emulate respective partitions of a circuit design and/or to perform other functions.

Abstract: An emulation system can include a first integrated circuit (IC) including first circuitry and a first transceiver. The first circuitry is configured to emulate a first partition of a circuit design. The first circuitry is clocked by an emulation clock and the first transceiver is clocked by a transceiver clock asynchronous with the emulation clock. The transceiver clock has a higher frequency than the emulation clock. The emulation system can include a second IC configured to emulate a second partition of the circuit design. The second IC includes a second transceiver. The first transceiver is configured to generate multiplexed emulation data by multiplexing a plurality of nets that cross from the first partition to the second partition of the circuit design. The first transceiver is configured to send the multiplexed emulation data over a serial communication channel to the second transceiver. The multiplexed emulation data includes a clock signal of the first transceiver embedded therein.

Abstract: Systems and methods can operate to transmit embedded control data (ECD) information within the payload of packet data. Payload packet data can contain a plurality of data elements of equal value. A transmitter can replace the repeating data elements with ECD information. A receiver can extract the ECD information and replace with the repeating data value to reconstruct the original. ECD information can be communicated between communication systems and between interfaces within a communication system.

Abstract: Devices, systems and methods of this disclosure can provide integrated circuit devices operating above their specified operating temperate. The integrated circuit device can include functional blocks with power down circuitry and functional test blocks with built in self-test capabilities (BIST). The functional blocks can be implemented with timing constraint values to provide a timing margin for the device above a specified operation temperature. The functional test blocks can be implemented with timing constraint values that result in BIST failure when the device is operated above the specified operation temperature. As the temperature of the device rises above the operating temperature the functional test blocks can fail BIST prior to loss of functionality of the functional blocks. Upon BIST failure of the functional test blocks, circuitry in the functional blocks can be powered down to facilitate continued operation of the device with reduced functionality.

Abstract: The Swivel Flosser comprises of these parts: a handle portion which is used to hold the flosser, a head portion which grasps the dental floss and has a u shaped configuration. The dental floss is part of the head portion. The head and the handle can be assembled by the user, once assembled together the head can rotate with respect to the handle allowing the user to clean the front teeth, the molars and everything in between with ease. The handle as well as the head can both be disposable or reusable according to utility and personal preference.