Patents by Inventor Taul Katayama

Taul Katayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7733889
    Abstract: A network switching device that prevents its shared buffer from suffering a blocking problem, while achieving a higher memory use efficiency in buffering variable-length packets. Every received packet is divided into one or more fixed-length data blocks and supplied to the buffer. Under the control of a buffer controller, a transmit queue is created to store up to a fixed number of data blocks for each different destination network, and the data blocks written in the buffer are registered with a transmit queue corresponding to a given destination. The linkage between data blocks in each packet, as well as the linkage between packets in each transmit queue, is managed as a linked list structure based on the locations of data blocks in the buffer.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: June 8, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Taul Katayama
  • Patent number: 7620054
    Abstract: A network switching device is provided for enabling priority control of packets, enhancing the using efficiency of a buffer for storing a received packet, and reducing the costs of components. The received packet is stored in the corresponding buffer with information of the packet under the control of a buffer controller. Further, a priority determining circuit is also provided for determining a priority class and a destination of the received packet. The buffer controller creates a transmit queue to which the packets of priority classes are to be registered in each buffer. When writing the received packet in the buffer, the buffer controller is served to reserve the received packet for transmission next to the last registered one of the packets of the same priority class registered in the corresponding transmit queue based on the determination of the priority determining circuit.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: November 17, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Taul Katayama
  • Publication number: 20050163141
    Abstract: A network switching device that prevents its shared buffer from suffering a blocking problem, while achieving a higher memory use efficiency in buffering variable-length packets. Every received packet is divided into one or more fixed-length data blocks and supplied to the buffer. Under the control of a buffer controller, a transmit queue is created to store up to a fixed number of data blocks for each different destination network, and the data blocks written in the buffer are registered with a transmit queue corresponding to a given destination. The linkage between data blocks in each packet, as well as the linkage between packets in each transmit queue, is managed as a linked list structure based on the locations of data blocks in the buffer.
    Type: Application
    Filed: March 18, 2005
    Publication date: July 28, 2005
    Applicant: FUJITSU LIMITED
    Inventor: Taul Katayama
  • Publication number: 20050129044
    Abstract: A network switching device is provided for enabling priority control of packets, enhancing the using efficiency of a buffer for storing a received packet, and reducing the costs of components. The received packet is stored in the corresponding buffer with information of the packet under the control of a buffer controller. Further, a priority determining circuit is also provided for determining a priority class and a destination of the received packet. The buffer controller creates a transmit queue to which the packets of priority classes are to be registered in each buffer. When writing the received packet in the buffer, the buffer controller is served to reserve the received packet for transmission next to the last registered one of the packets of the same priority class registered in the corresponding transmit queue based on the determination of the priority determining circuit.
    Type: Application
    Filed: February 2, 2005
    Publication date: June 16, 2005
    Applicant: FUJITSU LIMITED
    Inventor: Taul Katayama
  • Publication number: 20030204653
    Abstract: A network switching device which can guarantee transfer quality of packets having high priority. A priority determination circuit determines a priority of received data when the received data is input. An amount-of-use detection circuit determines whether or not an amount of current use of a buffer exceeds a threshold value which is associated with each priority in advance. A data transfer circuit stores the received data in the buffer when the amount of current use of the buffer does not exceed the threshold value associated with the priority of the received data. Thus, it is possible to store only received data having high priority in the buffer when free capacity of the buffer becomes small.
    Type: Application
    Filed: January 27, 2003
    Publication date: October 30, 2003
    Applicant: Fujitsu Limited
    Inventor: Taul Katayama