Abstract: Hardware test systems are provided that have an electrical test loop with a minimum length of less than 200 mm, a maximum di/dt capacity of at least 1500 A/?s and a minimum parasitic inductance of less than 100 nH. The hardware tests systems can be used for commutation measurement or other test applications requiring low stray inductance.

Abstract: Hardware test systems are provided that have an electrical test loop with a minimum length of less than 200 mm, a maximum di/dt capacity of at least 1500A/?s and a minimum parasitic inductance of less than 100 nH. The hardware tests systems can be used for commutation measurement or other test applications requiring low stray inductance.

Abstract: The invention includes stacked die packages. In one implementation, a stacked die package includes a base substrate and at least two pairs of flip chip stacks. Each pair comprises a flip chip in die up orientation, a flip chip in die down orientation and an interposer substrate to which the die up and die down flip chips electrically connect. A first of the at least two pairs of flip chip stacks is adhesively bonded to the base substrate. A second of the at least two pairs of flip chip stacks is adhesively bonded to the first pair of flip chip stacks by an insulative adhesive. Electrically conductive interconnects electrically connect the interposer substrates of at least the first and second stacks with the base substrate. Other aspects and implementations are contemplated.