Abstract: A readout circuit that allows on-chip bias calibration of a microbolometer focal plane array (FPA). The readout circuit includes a memory for storing one or more biasing values for a plurality of pixels within the FPA, the plurality of pixels being arranged in one or more columns and one or more rows within the FPA. The readout circuit further includes a column readout connected to the memory and configured to search for the one or more biasing values and to apply a bias adjustment based on the one or more biasing values to a signal received from the FPA. The readout circuit further includes a column multiplexer connected to the column readout and configured to perform dynamic column selection for one or more columns of pixels within the FPA.

Abstract: Methods, systems, and apparatus to manufacture a microbolometer detector in a standard CMOS foundry. The method includes forming a Complementary Metal Oxide Semiconductor (CMOS) wafer including a silicon substrate layer, a metal stack, a dielectric layer, and a thermoelectric conversion element embedded in the dielectric layer. The metal stack includes at least two metal layers in contact with each other. The metal stack and the dielectric layer are on the silicon substrate layer. The thermoelectric conversion element is configured to convert heat into an electrical signal. The method includes etching the metal stack to define exterior lateral edges of a microbolometer bridge including at least a portion of the dielectric layer and the thermoelectric conversion element embedded in the dielectric layer. The method includes etching the silicon substrate layer beneath the microbolometer bridge.

Abstract: Methods, systems, and apparatus to manufacture a microbolometer detector in a standard CMOS foundry. The method includes forming a Complementary Metal Oxide Semiconductor (CMOS) wafer including a silicon substrate layer, a metal stack, a dielectric layer, and a thermoelectric conversion element embedded in the dielectric layer. The metal stack includes at least two metal layers in contact with each other. The metal stack and the dielectric layer are on the silicon substrate layer. The thermoelectric conversion element is configured to convert heat into an electrical signal. The method includes etching the metal stack to define exterior lateral edges of a microbolometer bridge including at least a portion of the dielectric layer and the thermoelectric conversion element embedded in the dielectric layer. The method includes etching the silicon substrate layer beneath the microbolometer bridge.

Abstract: A readout circuit that allows on-chip bias calibration of a microbolometer focal plane array (FPA). The readout circuit includes a memory for storing one or more biasing values for a plurality of pixels within the FPA, the plurality of pixels being arranged in one or more columns and one or more rows within the FPA. The readout circuit further includes a column readout connected to the memory and configured to search for the one or more biasing values and to apply a bias adjustment based on the one or more biasing values to a signal received from the FPA. The readout circuit further includes a column multiplexer connected to the column readout and configured to perform dynamic column selection for one or more columns of pixels within the FPA.

Abstract: This invention is related with electrical energy conversion device, which uses built-in potential of metal-to-metal junctions from repeating movements with random frequencies, speeds and amplitudes at the medium of the device. The device using the method does not rely on a resonant frequency, besides, it can convert the kinetic energy to electrical energy even at low frequencies. Furthermore, its application to the real life situations is economic and beneficial because of the efficient working principle and simple structure. Unique design of the device enables direct wiring of the outputs of identical or similar devices together for the purpose of power scaling without the need of using another device, which may cause energy losses and increase the total cost. This device also does not require a dummy voltage source or a precharge at the beginning of energy harvesting.

Abstract: A wafer-level packaging method for MEMS structures that are desired to be encapsulated in a hermetic cavity and that need the transfer of at least a single or multiple electrical leads to the outside of the cavity without destroying the hermeticity of the cavity. Lead transfer is achieved using vertical feedthroughs that are patterned on the capping substrate within the same fabrication step to produce the encapsulating cavity. Furthermore, the structure of the vertical feedthroughs and via openings to reach these feedthroughs are arranged in such a way that conventional wirebonding would be sufficient to connect the vertical feedthroughs to the outer world, without a need for conductor-refill inside the via openings. The method is compatible with low-temperature thermocompression-based bonding/sealing processes using various sealing materials such as thin-film metals and alloys, and also with the silicon-glass anodic or silicon-silicon fusion bonding processes.

Abstract: A wafer-level packaging method for MEMS structures that are desired to be encapsulated in a hermetic cavity and that need the transfer of at least a single or multiple electrical leads to the outside of the cavity without destroying the hermeticity of the cavity. Lead transfer is achieved using vertical feedthroughs that are patterned on the capping substrate within the same fabrication step to produce the encapsulating cavity. Furthermore, the structure of the vertical feedthroughs and via openings to reach these feedthroughs are arranged in such a way that conventional wirebonding would be sufficient to connect the vertical feedthroughs to the outer world, without a need for conductor-refill inside the via openings. The method is compatible with low-temperature thermocompression-based bonding/sealing processes using various sealing materials such as thin-film metals and alloys, and also with the silicon-glass anodic or silicon-silicon fusion bonding processes.

Abstract: This disclosure discusses various methods for manufacturing uncooled infrared detectors by using foundry-defined silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) wafers, each of which may include a substrate layer, an insulation layer having a pixel region and a wall region surrounding the pixel region, a pixel structure formed on the pixel region of the insulation layer, a wall structure formed adjacent to the pixel structure and on the wall region of the insulation layer, a dielectric layer covering the pixel structure and the wall structure, a pixel mask formed within the dielectric layer and for protecting the pixel structure during a dry etching process, and a wall mask formed within the dielectric layer and for protecting the wall structure during the dry etching process, thereby releasing a space defined between the wall structure and the pixel structure after the dry etching process.

Abstract: This invention relates to techniques for controlling the amplitude and the insertion phase of an input signal in RF applications. More particularly, this invention relates to phase shifters, vector modulators, and attenuators employing both semi-conductor and RF microelectromechanical systems (MEMS) technologies.

Abstract: This disclosure discusses various methods for manufacturing uncooled infrared detectors by using foundry-defined silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) wafers, each of which may include a substrate layer, an insulation layer having a pixel region and a wall region surrounding the pixel region, a pixel structure formed on the pixel region of the insulation layer, a wall structure formed adjacent to the pixel structure and on the wall region of the insulation layer, a dielectric layer covering the pixel structure and the wall structure, a pixel mask formed within the dielectric layer and for protecting the pixel structure during a dry etching process, and a wall mask formed within the dielectric layer and for protecting the wall structure during the dry etching process, thereby releasing a space defined between the wall structure and the pixel structure after the dry etching process.

Abstract: Micromachined, CMOS p+-active/n-well diodes are used as infrared sensing elements in uncooled Focal Plane Arrays (FPA). The FPAs are fabricated using a standard CMOS process followed by post-CMOS bulk-micromachining steps without any critical lithography or complicated deposition processes. Micromachining steps include Reactive Ion Etching (RIE) to reach the bulk silicon and anisotropic silicon wet etching together with electrochemical etch-stop technique to obtain thermally isolated p+-active/n-well diodes. The FPAs are monolithically integrated with their readout circuit since they are fabricated in any standard CMOS technology.