Abstract: A processor includes an array of resistive processing units connected between row and column lines with a resistive element. A first single instruction, multiple data processing unit (SIMD) is connected to the row lines. A second SIMD is connected to the column lines. A first instruction issuer is connected to the first SIMD to issue instructions to the first SIMD, and a second instruction issuer is connected to the second SIMD to issue instructions to the second SIMD such that the processor is programmable and configurable for specific operations depending on an issued instruction set.

Abstract: A processing unit, including a first circuit, and a first circuit element connected to the first circuit. The first circuit element is at least charged by the first circuit.

Abstract: A resistive processing unit (RPU) that includes a pair of transistors connected in series providing an update function for a weight of a training methodology to the RPU, and a read transistor for reading the weight of the training methodology. In some embodiments, the resistive processing unit (RPU) further includes a capacitor connecting a gate of the read transistor to the air of transistors providing the update function for the resistive processing unit (RPU). The capacitor stores said weight of training methodology for the RPU.

Abstract: A resistive processing unit (RPU) that includes a pair of transistors connected in series providing an update function for a weight of a training methodology to the RPU, and a read transistor for reading the weight of the training methodology. In some embodiments, the resistive processing unit (RPU) further includes a capacitor connecting a gate of the read transistor to the air of transistors providing the update function for the resistive processing unit (RPU). The capacitor stores said weight of training methodology for the RPU.

Abstract: A system comprises a processor, and a resistive processing resistive processing unit coupled to the processor. The resistive processing unit comprises an array of cells, wherein the cells respectively comprise resistive memory devices, wherein at least a portion of the resistive memory devices are programmable to store weight values of a given matrix in the array of cells. The processor is configured to store the given matrix in the array of cells of the resistive processing unit, and perform a calibration process to generate a first set of calibration parameters for calibrating forward pass matrix-vector multiplication operations performed on the stored matrix in the array of cells of the resistive processing unit, and a second set of calibration parameters for calibrating backward pass matrix-vector multiplication operations performed on a transpose of the stored matrix in the array of cells of the resistive processing unit.

Abstract: Techniques facilitating automatic non-linearity correction for analog hardware are provided. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an adjustment component that determines a non-linear correction term for an output of an array of analog memories based on a result of a matrix vector multiplication performed on the array of analog memories. The computer executable components can also comprise a rectification component that applies the non-linear correction term to additional outputs of the array of analog memories.

Abstract: A system comprises compute nodes distributed over a network and configured to perform a pipeline parallel process. The system also comprises an extended memory comprising a global virtual address space which is shared by the compute nodes. The extended memory is configured to enable the compute nodes to exchange data over the network when the compute nodes perform the pipeline parallel process.

Abstract: Machine learning is enhanced by efficiently updating a weight that is represented as a conductivity of a resistive processing unit (RPU) that is connected between a row wire and a column wire. The weight is updated by the RPU interacting with bit streams carried on the row and column wires. Efficiency of the update is enhanced by calculating a bit length for the bit streams as a function of factors that include learning rate ?, maximum activity xmax, maximum error differential ?max, and minimum weight update increment ?wmin.

Abstract: A method for multiple copies of a set of multi-kernel set operations in a hardware accelerated neural network includes a word line for receiving a pixel value of an input image. A bit line communicates a modified pixel value. An analog memory cell including a first capacitor stores a first kernel weight of a first kernel in one of a plurality of kernel sets such that the pixel value is operated on by the first kernel weight to produce the modified pixel value. A charge connection connects the first capacitor to at least a second capacitor storing a second kernel weight of a related kernel of a second one of the plurality of kernel sets such that charge is shared between the first capacitor and at least the second capacitor to normalize the first kernel weight and the second kernel weight.

Abstract: Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating analog crossbar arrays. The embodiments include receiving a number used in matrix multiplication to represent using pulse generation for a crossbar array, and receiving a first bit-length to represent the number, wherein the bit-length is a modifiable bit length. The embodiments also include selecting pulse positions in a pulse sequence having the first bit length to represent the number, performing a computation using the selected pulse positions in the pulse sequence, and updating the crossbar array using the computation.

Abstract: In a method of training a DNN, a weight matrix (W) is provided as a linear combination of matrices/arrays A and C. In a forward cycle, an input vector x is transmitted through arrays A and C and output vector y is read. In a backward cycle, an error signal ? is transmitted through arrays A and C and output vector z is read. Array A is updated by transmitting input vector x and error signal ? through array A. In a forward cycle, an input vector ei is transmitted through array A and output vector y? is read. ƒ(y?) is calculated using y?. Array C is updated by transmitting input vector ei and ƒ(y?) through array C. A DNN is also provided.

Abstract: Techniques for auto weight scaling a bounded weight range of RPU devices with the size of the array during ANN training are provided. In one aspect, a method of ANN training includes: initializing weight values winit in the array to a random value, wherein the array represents a weight matrix W with m rows and n columns; calculating a scaling factor ? based on a size of the weight matrix W; providing digital inputs x to the array; dividing the digital inputs x by a noise and bound management factor ? to obtain adjusted digital inputs x?; performing a matrix-vector multiplication of the adjusted digital inputs x? with the array to obtain digital outputs y?; multiplying the digital outputs y? by the noise and bound management factor ?; and multiplying the digital outputs y? by the scaling factor ? to provide digital outputs y of the array.

Abstract: Methods and systems for solving a linear system include setting resistances in an array of settable electrical resistances in accordance with values of an input matrix. A series of input vectors is applied to the array as voltages to generate a series of respective output vectors. Each input vector in the series of vectors is updated based on comparison of the respective output vectors to a target vector. A solution of a linear system is determined that includes the input matrix based on the updated input vectors.

Abstract: A system includes a processor, and a resistive processing resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells, wherein the cells respectively include resistive devices, wherein at least a portion of the resistive devices are programmable to store weight values of a given matrix in the array of cells. When the given matrix is stored in the array of cells, the processor is configured to perform a weight extraction process. The weight extraction process applies a set of input vectors to the resistive processing unit to perform analog matrix-vector multiplication operations on the stored matrix, obtains a set of output vectors resulting from the analog matrix-vector multiplication operations, and determines weight values of the given matrix stored in the array of cells utilizing the set of input vectors and the set of output vectors.

Abstract: A computer-implemented method is presented for performing matrix sketching by employing an analog crossbar architecture. The method includes low rank updating a first matrix for a first period of time, copying the first matrix into a dynamic correction computing device, switching to a second matrix to low rank update the second matrix for a second period of time, as the second matrix is low rank updated, feeding the first matrix with first stochastic pulses to reset the first matrix back to a first matrix symmetry point, copying the second matrix into the dynamic correction computing device, switching back to the first matrix to low rank update the first matrix for a third period of time, and as the first matrix is low rank updated, feeding the second matrix with second stochastic pulses to reset the second matrix back to a second matrix symmetry point.

Abstract: Techniques are provided to implement hardware accelerated computing of eigenpairs of a matrix. For example, a system includes a processor, and a resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells which include respective resistive devices, wherein at least a portion of the resistive devices are tunable to encode values of a given matrix which is storable in the array of cells. When the given matrix is stored in the array of cells, the processor is configured to determine an eigenvector of the stored matrix by executing a process which includes performing analog matrix-vector multiplication operations on the stored matrix to converge an initial vector to an estimate of the eigenvector of the stored matrix.

Abstract: A method is presented for computing an equilibrium distribution of Markov processes. The method includes storing weight values in an analog crossbar array of transition probability matrices, where the analog crossbar array of transition probability matrices represents a weight matrix with m rows and n columns, computing an eigenvector associated with a real eigenvalue of modulus one for each of the transition probability matrices, applying a gradient-based eigenvalue solver to converge to a dominant eigenpair, and determining a probability of changing from one state to another state in a stochastic entity based on outcomes of the gradient-based eigenvalue solver.

Abstract: A device configured to implement an artificial intelligence deep neural network includes a first matrix and a second matrix. The first matrix resistive processing unit (“RPU”) array receives a first input vector along the rows of the first matrix RPU. A second matrix RPU array receives a second input vector along the rows of the second matrix RPU. A reference matrix RPU array receives an inverse of the first input vector along the rows of the reference matrix RPU and an inverse of the second input vector along the rows of the reference matrix RPU. A plurality of analog to digital converters are coupled to respective outputs of a plurality of summing junctions that receive respective column outputs of the first matrix RPU array, the second matrix RPU array, and the reference RPU array and provides a digital value of the output of the plurality of summing junctions.

Abstract: Cross-point arrays and methods of updating values of the same include input resistive processing units (RPUs), each having a settable resistance, each connected to a common node. Output RPUs each have a settable resistance and are each connected to the common node. An update switch is configured to connect an update voltage to the common node.

Abstract: Embodiments disclosed herein include a method of training a DNN. A processor initializes an element of an A matrix. The element may include a resistive processing unit. A processor determines incremental weight updates by updating the element with activation values and error values from a weight matrix multiplied by a chopper value. A processor reads an update voltage from the element. A processor determines a chopper product by multiplying the update voltage by the chopper value. A processor stores an element of a hidden matrix. The element of the hidden matrix may include a summation of continuous iterations of the chopper product. A processor updates a corresponding element of a weight matrix based on the element of the hidden matrix reaching a threshold state.