Abstract: The present disclosure relates to applying genetic optimization to a routing strategy associated with an electronic design. Embodiments may include receiving pin and net information from an electronic design file and determining a minimum spanning tree for all pins associated with each net. Embodiments may include identifying pairs of connected pins and representing the pins as at least one line segment without layer information. Embodiments may include generating a crossing map based upon the line segments and assigning random layer information to each of the line segments. Embodiments may further include performing crossover and mutation operations to the line segments using hyperparameters and evaluating a fitness of the line segments. Embodiments may also include instantiating vias based upon a layer to which the line segment was assigned.

Abstract: The present disclosure relates to systems and methods for floorplanning using machine learning techniques. Embodiments may include receiving an electronic design and analyzing the electronic design using a reinforcement learning agent. Embodiments may further include recommending a first action wherein the first action includes at least one of a place agent action, a via agent action, or a route agent action. Embodiments may also include updating the electronic design based upon, at least in part, the first action to generate an updated electronic design. Embodiments may further include analyzing the updated electronic design using the reinforcement learning agent and recommending a second action wherein the second action includes at least one of a place agent action, a via agent action, or a route agent action. Embodiments may also include updating the updated electronic design based upon the second action to generate a second updated electronic design.

Abstract: Apparatus for evaluating a design includes a memory for storing data representing a current design for the device; a host processor connected to the memory and having a change input for receiving an input signal representing a change in the design, an event output for generating an event signal representing at least that a change has occurred; a plurality of advisors, each advisor having an event input for receiving the event signal; a data input connected to the memory, an advisor processor for generating scoring signals representing a selected quality of the design, and presenting the scoring signal to an advisor scoring output; an advisor backplane connected between the host processor and the advisors, the advisor backplane having an event input coupled to the host processor for receiving event signals, an event output coupled to the advisors' event inputs, and a scoring input connected to the advisors' scoring outputs for receiving the scoring signals from the advisors and for combining the scores for gen