Abstract: A method of processing data is disclosed that includes performing a fetch of a plurality of instructions from a memory unit. The method also includes grouping the plurality of instructions into packets of instructions of different types for parallel execution by a plurality of instruction execution units. The packets of instructions include a first instruction and a second instruction. The method includes using a combined scalar and vector condition code register to execute the first instruction for a compare operation and the second instruction for a conditional operation using the combined scalar and vector condition code register. The method also includes when the compare operation is a scalar compare operation, receiving a scalar compare instruction for the scalar compare operation at an instruction executing unit and storing results of the scalar compare operation in the combined scalar and vector condition code register.

Abstract: A multithreaded processor device is disclosed and includes a processor that is configured to execute a plurality of executable program threads and a mode control register. The mode control register includes a first data field to control a first execution mode of a first of the plurality of executable program threads and a second data field to control a second execution mode of a second of the plurality of executable program threads. In a particular embodiment, the first execution mode is a run mode and the second execution mode is a low power mode.

Abstract: A method of processing data is disclosed that includes performing a fetch of a plurality of instructions from a memory unit. The method also includes grouping the plurality of instructions into packets of instructions of different types for parallel execution by a plurality of instruction execution units. The packets of instructions include a first instruction and a second instruction. The method includes using a combined scalar and vector condition code register to execute the first instruction for a compare operation and the second instruction for a conditional operation using the combined scalar and vector condition code register. The method also includes when the compare operation is a scalar compare operation, receiving a scalar compare instruction for the scalar compare operation at an instruction executing unit and storing results of the scalar compare operation in the combined scalar and vector condition code register.

Abstract: A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a compare operation can store resulting bits in the combined condition code register and a conditional operation can utilize the combined condition code register bits for evaluating a condition.

Abstract: A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a compare operation can store resulting bits in the combined condition code register and a conditional operation can utilize the combined condition code register bits for evaluating a condition.

Abstract: A multithreaded processor device is disclosed and includes a processor that is configured to execute a plurality of executable program threads and a mode control register. The mode control register includes a first data field to control a first execution mode of a first of the plurality of executable program threads and a second data field to control a second execution mode of a second of the plurality of executable program threads. In a particular embodiment, the first execution mode is a run mode and the second execution mode is a low power mode.

Abstract: A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit responsive to the sequencer, a third instruction execution unit responsive to the sequencer, and a fourth instruction execution unit responsive to the sequencer. Further, the processor device includes a plurality of register files and each of the plurality of register files includes a plurality of registers. The plurality of register files are coupled to the sequencer and coupled to the first instruction execution unit, the second instruction execution unit, the third instruction execution unit, and the fourth instruction execution unit.