Patents by Inventor Te-An Tsai
Te-An Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996325Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.Type: GrantFiled: July 29, 2020Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
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Patent number: 11990167Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.Type: GrantFiled: June 21, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bo-Jhih Shen, Kuang-I Liu, Joung-Wei Liou, Jinn-Kwei Liang, Yi-Wei Chiu, Chin-Hsing Lin, Li-Te Hsu, Han-Ting Tsai, Cheng-Yi Wu, Shih-Ho Lin
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Patent number: 11988553Abstract: An optical module is disclosed. The optical module includes a carrier, an optical emitter disposed over the carrier, and a monitor disposed over the carrier and configured to adjust a property of a first light emitted from the optical emitter.Type: GrantFiled: September 20, 2022Date of Patent: May 21, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Kuo Sin Huang, Tien-Chia Liu, Ko-Fan Tsai, Cheng-Te Chou, Yan-Te Chou
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Publication number: 20240162318Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.Type: ApplicationFiled: January 26, 2024Publication date: May 16, 2024Inventors: Min-Kun DAI, Wei-Gang CHIU, I-Cheng CHANG, Cheng-Yi WU, Han-Ting TSAI, Tsann LIN, Chung-Te LIN
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Patent number: 11984508Abstract: A thin film transistor includes an active layer and at least one gate stack. The active layer may be formed using multiple iterations of a unit layer stack deposition process, which includes an acceptor-type oxide deposition process and a post-transition metal oxide deposition process. A surface of each gate dielectric within the at least one gate stack contacts a surface of a respective layer of the oxide of the acceptor-type element so that leakage current of the active layer may be minimized. A source electrode and a drain electrode may contact an oxide layer providing lower contact resistance such as a layer of the post-transition metal oxide or a zinc oxide layer within the active layer.Type: GrantFiled: September 8, 2021Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wu-Wei Tsai, Po-Ting Lin, Hai-Ching Chen, Chung-Te Lin
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Patent number: 11985906Abstract: A magnetic tunnel junction (MTJ) memory cell and a metallic etch mask portion are formed over a substrate. At least one dielectric etch stop layer is deposited over the metallic etch mask portion, and a via-level dielectric layer is deposited over the at least one dielectric etch stop layer. A via cavity may be etched through the via-level dielectric layer, and a top surface of the at least one dielectric etch stop layer is physically exposed. The via cavity may be vertically extended by removing portions of the at least one dielectric etch stop layer and the metallic etch mask portion. A contact via structure is formed directly on a top surface of the top electrode in the via cavity to provide a low-resistance contact to the top electrode.Type: GrantFiled: March 12, 2021Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Feng Yin, Tai-Yen Peng, An-Shen Chang, Han-Ting Tsai, Qiang Fu, Chung-Te Lin
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Publication number: 20240155185Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.Type: ApplicationFiled: November 9, 2022Publication date: May 9, 2024Inventors: Chia-Hao CHANG, You-Tsai JENG, Kai-Wen YEH, Yi-Cheng CHEN, Te-Chuan WANG, Kai-Wen CHENG, Chin-Lung LIN, Tai-Lai TUNG, Ko-Yin LAI
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Patent number: 11978675Abstract: A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.Type: GrantFiled: November 22, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Ming-Te Chen, Tien-Wei Yu
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Publication number: 20240145571Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.Type: ApplicationFiled: January 5, 2023Publication date: May 2, 2024Inventors: Po-Ting Lin, Yu-Ming Hsiang, Wei-Chih Wen, Yin-Hao Wu, Wu-Wei Tsai, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
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Publication number: 20240142428Abstract: A water quality detection device including a detection tank, a sensor, the cleaner and a processor is provided. The sensor is disposed on the detection tank and is configured to sense a to-be-detected liquid within the detection tank. The cleaner is configured to clean the sensor. The processor is electrically connected to the sensor and the cleaner and is configured to: execute an initialization procedure, which includes driving the sensor to sense the to-be-detected liquid to obtain a number of initial sensing values and calculating a threshold value according to the initial sensing values; drive the sensor to sense the to-be-detected liquid to obtain a sensing value of the to-be-detected liquid, and determine whether the sensing value of the to-be-detected liquid reaches the threshold value; drive the cleaner to operate when the sensing value of the to-be-detected liquid reaches the threshold value.Type: ApplicationFiled: February 17, 2023Publication date: May 2, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Tsung-Yu TSAI, Hung-Sheng LIN, Cheng-Da KO, Chun-Te CHUANG
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Patent number: 11968843Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.Type: GrantFiled: February 7, 2019Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Te Lin, Yen-Chung Ho, Pin-Cheng Hsu, Han-Ting Tsai, Katherine Chiang
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Patent number: 11962847Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.Type: GrantFiled: November 9, 2022Date of Patent: April 16, 2024Assignee: MEDIATEK INC.Inventors: Chia-Hao Chang, You-Tsai Jeng, Kai-Wen Yeh, Yi-Cheng Chen, Te-Chuan Wang, Kai-Wen Cheng, Chin-Lung Lin, Tai-Lai Tung, Ko-Yin Lai
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Publication number: 20240113222Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.Type: ApplicationFiled: January 3, 2023Publication date: April 4, 2024Inventors: Yan-Yi Chen, Wu-Wei Tsai, Yu-Ming Hsiang, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
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Publication number: 20240113225Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.Type: ApplicationFiled: January 10, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wu-Wei Tsai, Yan-Yi Chen, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
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Patent number: 11948531Abstract: A light source device, including a first light source, providing a first light beam in a first time period of a first period; and a second light source, providing a second light beam in a second time period of the first period, is provided. The first light beam and the second light beam have the same color temperature. The first light beam and the second light beam are emitted alternately in the first period, and a color rendering index of mixed light of the first light beam and the second light beam is greater than or equal to 85.Type: GrantFiled: December 30, 2021Date of Patent: April 2, 2024Assignee: Industrial Technology Research InstituteInventors: Tzung-Te Chen, Hsin-Yun Tsai, Shih-Yi Wen, Chia-Fen Hsieh
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Publication number: 20240094052Abstract: An optical module is disclosed. The optical module includes a carrier, an optical emitter disposed over the carrier, and a monitor disposed over the carrier and configured to adjust a property of a first light emitted from the optical emitter.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Kuo Sin HUANG, Tien-Chia LIU, Ko-Fan TSAI, Cheng-Te CHOU, Yan-Te CHOU
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Patent number: 11935935Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.Type: GrantFiled: November 11, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Min-Kun Dai, Wei-Gang Chiu, I-Cheng Chang, Cheng-Yi Wu, Han-Ting Tsai, Tsann Lin, Chung-Te Lin
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Publication number: 20240086613Abstract: Disclosed herein are related to performing layout verification of a layout design of an integrated circuit having a slanted layout component. In one aspect, a slanted layout component having a side slanted from a base axis by an offset angle is detected. In one aspect, a first location of a vertex of the slanted layout component according to the offset angle is transformed to obtain a second location of a rotated vertex of a rotated layout component. In one aspect, layout verification is performed on the rotated layout component with respect to the base axis.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Te Hou, Min-Yuan Tsai
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Publication number: 20240081081Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.Type: ApplicationFiled: January 10, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Ling Lee, Chung-Te Lin, Han-Ting Tsai, Wei-Gang Chiu, Yen-Chieh Huang, Ming-Yi Yang
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Patent number: 11769625Abstract: A transformer apparatus reducing magnetic field interference includes an iron core, a first side coil unit, a second side coil unit, a first current transmission line, a second current transmission line and a third current transmission line. Both the first side coil unit and the second side coil unit are wound around the iron core. The first side coil unit is connected to the first current transmission line and the second current transmission line. The second current transmission line is connected to the third current transmission line. The first current transmission line includes a first current conduction segment and a first insulation layer. The first insulation layer coats the first current conduction segment. The third current transmission line includes a second current conduction segment and a second insulation layer. The second insulation layer coats the second current conduction segment. The second insulation layer touches the first insulation layer.Type: GrantFiled: December 8, 2020Date of Patent: September 26, 2023Assignee: P-DUKE TECHNOLOGY CO., LTD.Inventors: Lien-Hsing Chen, Cheng-Te Tsai, Sheng-Ken Huang