Patents by Inventor Te-An Wang

Te-An Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140365670
    Abstract: A distributed data processing system, a distributed data processing method and a wireless terminal point thereof are disclosed, where the distributed data process system includes a first access controller, a plurality of second access controllers and a wireless terminal point (WTP). When receiving a list containing address information of the second access controllers from the first access controller, the WTP selects one of the second access controllers to serve as a designated second access controller and connects the designated second access controller.
    Type: Application
    Filed: October 4, 2013
    Publication date: December 11, 2014
    Applicant: ACCTON TECHNOLOGY CORPORATION
    Inventors: Te-An WANG, Chun-Sen SUN, Chung-Jen CHEN, Tan-Chun LU
  • Patent number: 8019980
    Abstract: A branch target buffer (BTB) system and method for storing target address is provided. The BTB system is applicable to a 16-bit, 32-bit, 64-bit or higher processor architecture. When the target address of the branch instruction is stored, the BTB stores the variation range, carry bit and sub/add bit of the target address without having to store all the bits of the target address. Because the BTB does not need to store the identical part of the branch instruction address and the target address, the number of bits of the target address field for the BTB of the processor needs to be stored is reduced. Although less number of bits are stored for the target address field, the BTB system is able to generate a complete target address without affecting the computation performance.
    Type: Grant
    Filed: September 1, 2008
    Date of Patent: September 13, 2011
    Inventor: Te-An Wang
  • Publication number: 20100058038
    Abstract: A branch target buffer (BTB) system and method for storing target address is provided, applicable to a 16-bit, 32-bit, 64-bit or higher processor architecture. When storing the target address of the branch instruction, the BTB stores the variation range, carry bit and sub/add bit of the target address without having to store all the bits of the target address. Because the BTB of the present invention does not need to store the identical part of the branch instruction address and the target address, the present invention reduces the number of bits of the target address field for the BTB of the processor. Although the present invention uses less bits for target address field, the present invention is able to generate a complete target address without affecting the computation performance.
    Type: Application
    Filed: September 1, 2008
    Publication date: March 4, 2010
    Inventor: Te-An Wang