Patents by Inventor Te-An YU

Te-An YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12261203
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: March 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih Lin, Yun-Ju Pan, Szu-Chi Yang, Jhih-Yang Yan, Shih-Hao Lin, Chung-Shu Wu, Te-An Yu, Shih-Chiang Chen
  • Publication number: 20240395860
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih LIN, Yun-Ju PAN, Szu-Chi YANG, Jhih-Yang YAN, Shih-Hao LIN, Chung-Shu WU, Te-An YU, Shih-Chiang CHEN
  • Patent number: 11757018
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an n-type doped region in a semiconductor substrate and forming a semiconductor stack over the semiconductor substrate. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes introducing n-type dopants from the n-type doped region into the semiconductor stack during the forming of the semiconductor stack. The method further includes patterning the semiconductor stack to form a fin structure and forming a dummy gate stack to wrap around a portion of the fin structure. In addition, the method includes removing the dummy gate stack and the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor layers. The method includes forming a metal gate stack to wrap around the semiconductor nanostructures.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-An Yu, Hung-Ju Chou, Jet-Rung Chang, Yen-Po Lin, Jiun-Ming Kuo
  • Publication number: 20230122339
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.
    Type: Application
    Filed: January 19, 2022
    Publication date: April 20, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih LIN, Yun-Ju PAN, Szu-Chi YANG, Jhih-Yang YAN, Shih-Hao LIN, Chung-Shu Wu, Te-An YU, Shih-Chiang CHEN
  • Publication number: 20220384605
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an n-type doped region in a semiconductor substrate and forming a semiconductor stack over the semiconductor substrate. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes introducing n-type dopants from the n-type doped region into the semiconductor stack during the forming of the semiconductor stack. The method further includes patterning the semiconductor stack to form a fin structure and forming a dummy gate stack to wrap around a portion of the fin structure. In addition, the method includes removing the dummy gate stack and the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor layers. The method includes forming a metal gate stack to wrap around the semiconductor nanostructures.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-An YU, Hung-Ju CHOU, Jet-Rung CHANG, Yen-Po LIN, Jiun-Ming KUO