Patents by Inventor Te Bi

Te Bi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260088716
    Abstract: Switches are turned on and off to establish a first state in which a first capacitor is coupled between an input node and a first node, a second capacitor and a first coil are coupled between the first node and an output node, a third capacitor and a second coil are coupled between the first node and the output node, and a second node is coupled to a first reference potential node; and a second state in which the second capacitor and the first coil are coupled between a third node and the output node, the first and third capacitors and the second coil are coupled between the third node and the output node, a fourth node is coupled to a node to which the first and third capacitors are coupled, and a fifth node is coupled to a second reference potential node.
    Type: Application
    Filed: January 23, 2025
    Publication date: March 26, 2026
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Te BI, Chen Kong TEH
  • Patent number: 12457760
    Abstract: Provided are a diamond field effect transistor using a silicon oxide film as a gate insulating film including a silicon-terminated layer containing C—Si bonds in order to reduce an interface state density, and a method for producing the same. A FET 100A includes a silicon oxide film 3A formed on a surface of a non-doped diamond layer 2A, a non-doped diamond layer 4A formed on a surface of the non-doped diamond layer 2A using the silicon oxide film 3A as a mask, a silicon-terminated layer 5A formed at an interface between the non-doped diamond layer 2A and the silicon oxide film 3A and at an interface between the non-doped diamond layer 4A and the silicon oxide film 3A, and a gate electrode 12A formed on the silicon oxide film 3A. The FET 100A operates using the silicon oxide film 3A and an insulating film 10A formed on the silicon oxide film 3A as a gate insulating film 11A and using the non-doped diamond layer 4A as each of a source region and a drain region.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: October 28, 2025
    Assignee: Waseda University
    Inventors: Hiroshi Kawarada, Wenxi Fei, Te Bi, Masayuki Iwataki
  • Patent number: 12283890
    Abstract: A DCDC circuit according to an embodiment includes a capacitor network, and a smoothing capacitor. The capacitor network includes a first state in which first capacitors are connected onto a wiring path between an input node to which an input voltage is applied and one end of a first coil and a second capacitor is connected between a connection point of the first capacitors on the wiring path and a reference potential point, and a second state in which the second capacitor is connected to one end of a second coil and the first capacitors are connected between one end of the second capacitor and the reference potential point and between the other end of the second capacitor and the reference potential point, respectively.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: April 22, 2025
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Chen kong Teh, Te Bi
  • Publication number: 20230387804
    Abstract: A DCDC circuit according to an embodiment includes a capacitor network, and a smoothing capacitor. The capacitor network includes a first state in which first capacitors are connected onto a wiring path between an input node to which an input voltage is applied and one end of a first coil and a second capacitor is connected between a connection point of the first capacitors on the wiring path and a reference potential point, and a second state in which the second capacitor is connected to one end of a second coil and the first capacitors are connected between one end of the second capacitor and the reference potential point and between the other end of the second capacitor and the reference potential point, respectively.
    Type: Application
    Filed: February 2, 2023
    Publication date: November 30, 2023
    Inventors: Chen kong TEH, Te BI
  • Publication number: 20230136477
    Abstract: Provided are a diamond field effect transistor using a silicon oxide film as a gate insulating film including a silicon-terminated layer containing C—Si bonds in order to reduce an interface state density, and a method for producing the same. A FET 100A includes a silicon oxide film 3A formed on a surface of a non-doped diamond layer 2A, a non-doped diamond layer 4A formed on a surface of the non-doped diamond layer 2A using the silicon oxide film 3A as a mask, a silicon-terminated layer 5A formed at an interface between the non-doped diamond layer 2A and the silicon oxide film 3A and at an interface between the non-doped diamond layer 4A and the silicon oxide film 3A, and a gate electrode 12A formed on the silicon oxide film 3A. The FET 100A operates using the silicon oxide film 3A and an insulating film 10A formed on the silicon oxide film 3A as a gate insulating film 11A and using the non-doped diamond layer 4A as each of a source region and a drain region.
    Type: Application
    Filed: February 17, 2021
    Publication date: May 4, 2023
    Inventors: Hiroshi Kawarada, Wenxi Fei, Te Bi, Masayuki Iwataki
  • Patent number: 9842419
    Abstract: The disclosure discloses a method and device for display a picture, relates to the field of electronic information and is intended to address the problems of a long modeling period of time and inefficient modeling when the picture is three-dimensionally displayed. Particularly the method includes: obtaining at least one picture sequence number, wherein a picture sequence number corresponds to a picture; substituting the at least one picture sequence number into a preset set of equations to calculate location information of at least one picture, wherein the preset set of equations is a set of equations created in a virtual three-dimensional coordinate system, and location information of a picture corresponds to a picture sequence number; and displaying the at least one picture according to the location information of the at least one picture. The disclosure is applicable to display of a picture.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: December 12, 2017
    Assignees: HISENSE MOBILE COMMUNICATIONS TECHNOLOGY CO., LTD., HISENSE USA CORPORATION, HISENSE INTERNATIONAL CO., LTD.
    Inventor: Te Bi
  • Publication number: 20160063756
    Abstract: The disclosure discloses a method and device for display a picture, relates to the field of electronic information and is intended to address the problems of a long modeling period of time and inefficient modeling when the picture is three-dimensionally displayed. Particularly the method includes: obtaining at least one picture sequence number, wherein a picture sequence number corresponds to a picture; substituting the at least one picture sequence number into a preset set of equations to calculate location information of at least one picture, wherein the preset set of equations is a set of equations created in a virtual three-dimensional coordinate system, and location information of a picture corresponds to a picture sequence number; and displaying the at least one picture according to the location information of the at least one picture. The disclosure is applicable to display of a picture.
    Type: Application
    Filed: May 8, 2015
    Publication date: March 3, 2016
    Inventor: Te Bi