Abstract: A semiconductor device based on SiC-MOSFET realizes high voltage endurance, high current, low breakover voltage, low switching loss and low noise. The SiC-MOSFET is a combination of a Si-MOSFET with high channel mobility and a drift layer formed by SiC with high bulk mobility, so that the first conductive SiC wafer forming the drift layer joins the second conductive Si wafer, excavates out a trench gate in part of the SiC to make the MOSFET, and a second conductive barrier layer is arranged in the Si region adjacent to the SiC.

Abstract: A semiconductor device based on SiC-MOSFET realizes high voltage endurance, high current, low breakover voltage, low switching loss and low noise. The SiC-MOSFET is a combination of a Si-MOSFET with high channel mobility and a drift layer formed by SiC with high bulk mobility, so that the first conductive SiC wafer forming the drift layer joins the second conductive Si wafer, excavates out a trench gate in part of the SiC to make the MOSFET, and a second conductive barrier layer is arranged in the Si region adjacent to the SiC.

Abstract: A light source unit in a backlight module able to resist the accumulation of static electricity includes a circuit board, a plurality of lighting elements, a plurality of conductive lines, and at least one connecting line. Each conductive line electrically connects with lighting elements. The conductive line forms a plurality of first sharp portions. A plurality of second sharp portions which are grounded are facing the first sharp portions. The first sharp portions collect static electricity and the second sharp portions cooperate with the first sharp portions to discharge the static electricity.

Abstract: A cheap and high performance 1.5 transistor-type flash memory highly compatible externally of a memory region has a sacrifice film formed on a substrate. A U-shaped groove is formed on the sacrifice film, where multiple insulating films are laminated. The multiple insulating films includes a silicon nitride film as a charge storage layer. Low resistive material is disposed on the multiple insulating films to form a control gate. The select gate is formed on the insulating film on a side of the control gate in a self-aligned manner. Semiconductor regions opposite in conductivity to the substrate on both sides of the adjoining control gate and the select gate form a source and a drain, respectively. Thus, a 1.5 transistor-type flash memory is formed with the adjoining control gate and the select gate between the source and the drain.

Abstract: A light source unit in a backlight module able to resist the accumulation of static electricity includes a circuit board, a plurality of lighting elements, a plurality of conductive lines, and at least one connecting line. Each conductive line electrically connects with lighting elements. The conductive line forms a plurality of first sharp portions. A plurality of second sharp portions which are grounded are facing the first sharp portions. The first sharp portions collect static electricity and the second sharp portions cooperate with the first sharp portions to discharge the static electricity.

Abstract: A cheap and high performance 1.5 transistor-type flash memory highly compatible to external of memory region is provided. The flash memory has sacrifice film formed on substrate. U-shaped groove is formed on sacrifice film, where multiple insulating film is laminated. Multiple insulating film includes silicon nitride film as charge storage layer. Low resistive material is disposed on multiple insulating film to form control gate. Select gate is formed on insulating film on side of control gate in self-aligned manner. Semiconductor regions opposite in conductivity to substrate on both sides of adjoining control gate and select gate to form source and drain, respectively. Thus, a 1.5 transistor-type flash memory is formed with adjoining control gate and select gate between source and drain. In MOS-type transistor with control gate, threshold voltage is changeable according to injection/emission of charge to silicon nitride as charge storage layer, and thus work as non-volatile memory.

Abstract: A voltage adjusting circuit is provided. The voltage adjusting circuit for adjusting the output voltages supplied by voltage sources includes a test control device, a multiplexer, a comparator, and a built in self test (BIST) device. The test control device selects one of the voltage sources as a testing voltage source, and outputs a selecting command for selecting the testing voltage source and a target voltage corresponding to the testing voltage source. The multiplexer is coupled to the voltage sources, receives an enablement signal, and outputs a voltage supplied by the testing voltage source as a testing voltage according to the enablement signal. The comparator compares the voltage levels of the testing voltage and the target voltage, and outputs a comparison result.

Abstract: The invention provides a memory device on a substrate. The memory device comprises semiconductor layers, common word lines, common bit lines and a common source line. The semiconductor layers are stacked on the substrate, wherein each semiconductor layer has a plurality of NAND strings, and each NAND string includes memory cells and at least a string selection transistor. The common word lines are configured above the semiconductor layers, wherein each common word line is coupled to the memory cells arranged in a same row of the semiconductor layers. The common bit lines are configured on the common word lines, wherein each common bit line is coupled to a first ends of the NAND strings arranged in the same column of the semiconductor layers. The common source line is configured on the common word lines and coupled to a second ends of the NAND strings of the semiconductor layers.

Abstract: A memory device is provided. The memory device includes a memory array formed by a plurality of multi level cells, a determining circuit and a data reading circuit. The memory array includes a plurality of page units, each including a main data and an auxiliary data corresponding to the main data, wherein the auxiliary data includes a plurality of flag bits. The determining circuit generates a determination bit according to the flag bits. The data reading circuit obtains information corresponding to the main data according to the determination bit.

Abstract: The invention provides a memory device on a substrate. The memory device comprises semiconductor layers, common word lines, common bit lines and a common source line. The semiconductor layers are stacked on the substrate, wherein each semiconductor layer has a plurality of NAND strings, and each NAND string includes memory cells and at least a string selection transistor. The common word lines are configured above the semiconductor layers, wherein each common word line is coupled to the memory cells arranged in a same row of the semiconductor layers. The common bit lines are configured on the common word lines, wherein each common bit line is coupled to a first ends of the NAND strings arranged in the same column of the semiconductor layers. The common source line is configured on the common word lines and coupled to a second ends of the NAND strings of the semiconductor layers.

Abstract: An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the memory device after the end of the erasing period and includes a first and second switch circuit and a first and second control voltage supplier. The first switch circuit is coupled between the well voltage line, the first voltage line and a second supplier. The second switch circuit is coupled between the first switch circuit and a reference voltage. The first control voltage supplier is coupled to the first switch circuit and supplies a first control voltage to turn on the first switch circuit during a first discharge period. The second control voltage supplier is coupled to the second switch circuit, and supplies a second control voltage to turn on the second switch circuit during a second discharge period.

Abstract: A memory programming method is provided. A first programming operation is performed to program a multi level cell from an initial state to a first target state, which corresponds to a storage data and has a first threshold voltage range. A flag bit of the NAND flash is set to a first state to indicate that the first programming operation has been performed. A second programming operation is performed to program the multi level cell from the first target state to a second target state, which corresponds to the storage data and has a second threshold voltage range. The flag bit is set to a second state to indicate that the second programming operation has been performed.

Abstract: A flash memory and a regulated voltage generator thereof. The regulated voltage generator includes a charge pump having an output terminal outputting a first voltage, a control circuit coupled to the output terminal of the charge pump and having first and second output terminals outputting a second voltage and a charge pump control signal, respectively, and a Field Effect Transistor (FET) in diode mode. The FET is coupled between the output terminal of the charge pump and the first output terminal of the control circuit. The charge pump adjusts the first voltage according to the charge pump control signal.

Abstract: A memory device is provided. The memory device includes a memory array formed by a plurality of multi level cells, a determining circuit and a data reading circuit. The memory array includes a plurality of page units, each including a main data and an auxiliary data corresponding to the main data, wherein the auxiliary data includes a plurality of flag bits. The determining circuit generates a determination bit according to the flag bits. The data reading circuit obtains information corresponding to the main data according to the determination bit.

Abstract: A voltage adjusting circuit is provided. The voltage adjusting circuit for adjusting the output voltages supplied by voltage sources includes a test control device, a multiplexer, a comparator, and a built in self test (BIST) device. The test control device selects one of the voltage sources as a testing voltage source, and outputs a selecting command for selecting the testing voltage source and a target voltage corresponding to the testing voltage source. The multiplexer is coupled to the voltage sources, receives an enablement signal, and outputs a voltage supplied by the testing voltage source as a testing voltage according to the enablement signal. The comparator compares the voltage levels of the testing voltage and the target voltage, and outputs a comparison result.

Abstract: An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the memory device after the end of the erasing period and includes a first and second switch circuit and a first and second control voltage supplier. The first switch circuit is coupled between the well voltage line, the first voltage line and a second supplier. The second switch circuit is coupled between the first switch circuit and a reference voltage. The first control voltage supplier is coupled to the first switch circuit and supplies a first control voltage to turn on the first switch circuit during a first discharge period. The second control voltage supplier is coupled to the second switch circuit, and supplies a second control voltage to turn on the second switch circuit during a second discharge period.

Abstract: A memory programming method is provided. A first programming operation is performed to program a multi level cell from an initial state to a first target state, which corresponds to a storage data and has a first threshold voltage range. A flag bit of the NAND flash is set to a first state to indicate that the first programming operation has been performed. A second programming operation is performed to program the multi level cell from the first target state to a second target state, which corresponds to the storage data and has a second threshold voltage range. The flag bit is set to a second state to indicate that the second programming operation has been performed.