Patents by Inventor Te-Chih Chen

Te-Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11421105
    Abstract: A use of a low specific gravity PET composite material that is suitable for manufacturing a tableware article by injection molding is provided. The tableware article provides a balance between aesthetic appearance and food safety and can be used in place of melamine tableware. The low specific gravity PET composite material includes 66.5-96.3 wt % of PET, 0-20 wt % of PBT, 3-10 wt % of an inorganic filler, 0.1-0.5 wt % of an antioxidant, 0.1-1 wt % of a processing aid, and 0.5-2 wt % of a nucleating agent, and the total amount of all components is 100 wt %.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: August 23, 2022
    Assignee: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Han-Ching Hsu, Kai-Chih Lei, Chun-Lai Chen
  • Patent number: 11424364
    Abstract: A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xi-Zong Chen, Te-Chih Hsiung, Cha-Hsin Chao, Yi-Wei Chiu
  • Publication number: 20220216351
    Abstract: A method for manufacturing a sensing device is provided. The method includes: providing a substrate; forming a sensing unit on the substrate; forming a first light-shielding layer on the sensing unit; forming a first anti-reflection layer on the sensing unit; and patterning the first light-shielding layer and the first anti-reflection layer using a single lithography process to form a first pinhole corresponding to the sensing unit.
    Type: Application
    Filed: December 8, 2021
    Publication date: July 7, 2022
    Inventors: Wei-Lin WAN, Yu-Tsung LIU, Ming-Chih CHEN, Te-Yu LEE
  • Patent number: 10103248
    Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Tai-Ju Chen, Yi-Han Ye, Te-Chih Chen
  • Patent number: 9741830
    Abstract: The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and a part thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: August 22, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Publication number: 20170207322
    Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.
    Type: Application
    Filed: March 8, 2017
    Publication date: July 20, 2017
    Inventors: TAI-JU CHEN, YI-HAN YE, TE-CHIH CHEN
  • Patent number: 9640663
    Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: May 2, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Tai-Ju Chen, Yi-Han Ye, Te-Chih Chen
  • Publication number: 20160225880
    Abstract: The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and a part thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Application
    Filed: April 7, 2016
    Publication date: August 4, 2016
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Publication number: 20160155837
    Abstract: The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and apart thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Application
    Filed: December 27, 2014
    Publication date: June 2, 2016
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Publication number: 20160141420
    Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.
    Type: Application
    Filed: December 29, 2014
    Publication date: May 19, 2016
    Inventors: TAI-JU CHEN, YI-HAN YE, TE-CHIH CHEN
  • Patent number: 9337339
    Abstract: The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and apart thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: May 10, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Publication number: 20130169351
    Abstract: A transistor operating method is applicable to a transistor including a first gate, a first gate insulating layer, a semiconductor layer, a source, a drain, a second gate insulating layer and a second gate. The transistor operating method includes: grounding the first gate and the source, applying a negative bias to the second gate and applying a positive bias to the drain, so that the transistor acts as an optical detector; alternatively, grounding the source, grounding or floating the second gate, applying a bias to the first gate and applying a positive bias to the drain, so that the transistor acts as a pixel switch.
    Type: Application
    Filed: March 9, 2012
    Publication date: July 4, 2013
    Inventors: Ting-Chang CHANG, Te-Chih Chen, Fu-Yen Jian, Tien-Yu Hsieh
  • Patent number: 8427879
    Abstract: There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: April 23, 2013
    Assignee: Acer Incorporated
    Inventors: Ting-Chang Chang, Shih-Ching Chen, Te-Chih Chen, Fu-Yen Jian, Yong-En Syu
  • Patent number: 8339863
    Abstract: One embodiment of the present invention provides an operation method of a memory device. The memory device includes a source, a drain, and a channel region between the source and the drain, a gate dielectric with a charge storage layer on the channel region, and a gate on the gate dielectric, wherein the source, the drain and the channel region are located in a substrate. The operation method includes the following steps: applying a reverse bias between the gate and the drain of the memory device to generate band-to-band hot holes in the substrate near the drain; injecting the band-to-band hot holes to a drain side of the charge storage layer; and performing a program/erase operation upon the memory device. The band-to-band hot holes in the drain side of the charge storage layer are not completely vanished by the program/erase operation.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: December 25, 2012
    Assignee: Acer Incorporated
    Inventors: Ting-Chang Chang, Te-Chih Chen, Fu-Yen Jian, Chia-Sheng Lin
  • Patent number: 8208307
    Abstract: A method for operating a memory device is provided. In accordance with the method, the charges are stored in a source storage region, a drain storage region, and a channel storage region of a charge storage layer which respectively correspond to a source, a drain, and a channel of a SONOS transistor, thereby achieving 3-bit information storage in one cell. The channel storage region is programmed and erased by FN tunneling. Both of the source storage region and the drain storage region are programmed by channel hot electrons and erased by source-side or drain-side FN tunneling. The present invention can store three-bit data per cell, such that the storage density of the memory device can be substantially increased.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: June 26, 2012
    Assignee: Acer Incorporated
    Inventors: Ting-Chang Chang, Fu-Yen Jian, Shih-Ching Chen, Te-Chih Chen
  • Publication number: 20110205799
    Abstract: A method for operating a memory device is provided. In accordance with the method, the charges are stored in a source storage region, a drain storage region, and a channel storage region of a charge storage layer which respectively correspond to a source, a drain, and a channel of a SONOS transistor, thereby achieving 3-bit information storage in one cell. The channel storage region is programmed and erased by FN tunneling. Both of the source storage region and the drain storage region are programmed by channel hot electrons and erased by source-side or drain-side FN tunneling. The present invention can store three-bit data per cell, such that the storage density of the memory device can be substantially increased.
    Type: Application
    Filed: April 30, 2010
    Publication date: August 25, 2011
    Applicant: ACER INCORPORATED
    Inventors: Ting-Chang CHANG, Fu-Yen JIAN, Shih-Ching CHEN, Te-Chih CHEN
  • Patent number: 7983092
    Abstract: The present invention relates to a nonvolatile memory apparatus and a method of using a thin film transistor (TFT) as a nonvolatile memory by storing carriers in a body of the TFT, which operates a general TFT as a memory cell of a nonvolatile memory by manipulating the electrical characteristics of the TFT in order to integrate with other electrical components formed by TFTs, such as logic circuit or TFT-LCD pixel transistor, on the LCD panel without additional semiconductor manufacturing processes.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: July 19, 2011
    Assignee: Acer Incorporated
    Inventors: Ting-Chang Chang, Fu-Yen Jian, Te-Chih Chen
  • Publication number: 20110103155
    Abstract: One embodiment of the present invention provides an operation method of a memory device. The memory device includes a source, a drain, and a channel region between the source and the drain, a gate dielectric with a charge storage layer on the channel region, and a gate on the gate dielectric, wherein the source, the drain and the channel region are located in a substrate. The operation method includes the following steps: applying a reverse bias between the gate and the drain of the memory device to generate band-to-band hot holes in the substrate near the drain; injecting the band-to-band hot holes to a drain side of the charge storage layer; and performing a program/erase operation upon the memory device. The band-to-band hot holes in the drain side of the charge storage layer are not completely vanished by the program/erase operation.
    Type: Application
    Filed: July 22, 2010
    Publication date: May 5, 2011
    Applicant: ACER INCORPORATED
    Inventors: Ting-Chang Chang, Te-Chih Chen, Fu-Yen Jian, Chia-Sheng Lin
  • Publication number: 20110096610
    Abstract: There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor.
    Type: Application
    Filed: December 22, 2009
    Publication date: April 28, 2011
    Applicant: ACER INCORPORATED
    Inventors: Ting-Chang Chang, Shih-Ching Chen, Te-Chih Chen, Fu-Yen Jian, Yong-En Syu
  • Publication number: 20100254185
    Abstract: The present invention relates to a nonvolatile memory apparatus and a method of using a thin film transistor (TFT) as a nonvolatile memory by storing carriers in a body of the TFT, which operates a general TFT as a memory cell of a nonvolatile memory by manipulating the electrical characteristics of the TFT in order to integrate with other electrical components formed by TFTs, such as logic circuit or TFT-LCD pixel transistor, on the LCD panel without additional semiconductor manufacturing processes.
    Type: Application
    Filed: May 13, 2009
    Publication date: October 7, 2010
    Applicant: ACER INCORPORATED
    Inventors: Ting-Chang Chang, Fu-Yen Jian, Te-Chih Chen