Patents by Inventor Te-Chih Chen
Te-Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12211188Abstract: Image dewarping includes capturing a source image from a camera, selecting an input row of pixels from the source image, if the input row of pixels comprises a plurality of input pixels in a region of interest in the source image, storing the plurality of input pixels to a memory to generate an input segment of pixels, when a plurality of pixels required to generate an output row of pixels are all stored in the memory, reading from the memory the plurality of pixels corresponding to the output row of pixels, and performing coordinate transformation on the plurality of pixels to generate the output row of pixels, and when coordinate transformation has been completed on the plurality of pixels, releasing from the memory an input segment of pixels of the plurality of input segments of pixels that does not correspond to other output rows of pixels.Type: GrantFiled: February 24, 2022Date of Patent: January 28, 2025Assignee: WELTREND SEMICONDUCTOR INC.Inventors: Hsuan-Ying Chen, Hung-Chih Chiang, Ta Hsien, Te-Wei Hsu, Meng-Che Tsai
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Patent number: 10103248Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.Type: GrantFiled: March 8, 2017Date of Patent: October 16, 2018Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Tai-Ju Chen, Yi-Han Ye, Te-Chih Chen
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Patent number: 9741830Abstract: The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and a part thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.Type: GrantFiled: April 7, 2016Date of Patent: August 22, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
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Publication number: 20170207322Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.Type: ApplicationFiled: March 8, 2017Publication date: July 20, 2017Inventors: TAI-JU CHEN, YI-HAN YE, TE-CHIH CHEN
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Patent number: 9640663Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.Type: GrantFiled: December 29, 2014Date of Patent: May 2, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Tai-Ju Chen, Yi-Han Ye, Te-Chih Chen
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Publication number: 20160225880Abstract: The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and a part thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.Type: ApplicationFiled: April 7, 2016Publication date: August 4, 2016Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
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Publication number: 20160155837Abstract: The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and apart thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.Type: ApplicationFiled: December 27, 2014Publication date: June 2, 2016Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
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Publication number: 20160141420Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.Type: ApplicationFiled: December 29, 2014Publication date: May 19, 2016Inventors: TAI-JU CHEN, YI-HAN YE, TE-CHIH CHEN
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Patent number: 9337339Abstract: The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and apart thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.Type: GrantFiled: December 27, 2014Date of Patent: May 10, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
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Publication number: 20130169351Abstract: A transistor operating method is applicable to a transistor including a first gate, a first gate insulating layer, a semiconductor layer, a source, a drain, a second gate insulating layer and a second gate. The transistor operating method includes: grounding the first gate and the source, applying a negative bias to the second gate and applying a positive bias to the drain, so that the transistor acts as an optical detector; alternatively, grounding the source, grounding or floating the second gate, applying a bias to the first gate and applying a positive bias to the drain, so that the transistor acts as a pixel switch.Type: ApplicationFiled: March 9, 2012Publication date: July 4, 2013Inventors: Ting-Chang CHANG, Te-Chih Chen, Fu-Yen Jian, Tien-Yu Hsieh
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Patent number: 8427879Abstract: There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor.Type: GrantFiled: December 22, 2009Date of Patent: April 23, 2013Assignee: Acer IncorporatedInventors: Ting-Chang Chang, Shih-Ching Chen, Te-Chih Chen, Fu-Yen Jian, Yong-En Syu
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Patent number: 8339863Abstract: One embodiment of the present invention provides an operation method of a memory device. The memory device includes a source, a drain, and a channel region between the source and the drain, a gate dielectric with a charge storage layer on the channel region, and a gate on the gate dielectric, wherein the source, the drain and the channel region are located in a substrate. The operation method includes the following steps: applying a reverse bias between the gate and the drain of the memory device to generate band-to-band hot holes in the substrate near the drain; injecting the band-to-band hot holes to a drain side of the charge storage layer; and performing a program/erase operation upon the memory device. The band-to-band hot holes in the drain side of the charge storage layer are not completely vanished by the program/erase operation.Type: GrantFiled: July 22, 2010Date of Patent: December 25, 2012Assignee: Acer IncorporatedInventors: Ting-Chang Chang, Te-Chih Chen, Fu-Yen Jian, Chia-Sheng Lin
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Patent number: 8208307Abstract: A method for operating a memory device is provided. In accordance with the method, the charges are stored in a source storage region, a drain storage region, and a channel storage region of a charge storage layer which respectively correspond to a source, a drain, and a channel of a SONOS transistor, thereby achieving 3-bit information storage in one cell. The channel storage region is programmed and erased by FN tunneling. Both of the source storage region and the drain storage region are programmed by channel hot electrons and erased by source-side or drain-side FN tunneling. The present invention can store three-bit data per cell, such that the storage density of the memory device can be substantially increased.Type: GrantFiled: April 30, 2010Date of Patent: June 26, 2012Assignee: Acer IncorporatedInventors: Ting-Chang Chang, Fu-Yen Jian, Shih-Ching Chen, Te-Chih Chen
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Publication number: 20110205799Abstract: A method for operating a memory device is provided. In accordance with the method, the charges are stored in a source storage region, a drain storage region, and a channel storage region of a charge storage layer which respectively correspond to a source, a drain, and a channel of a SONOS transistor, thereby achieving 3-bit information storage in one cell. The channel storage region is programmed and erased by FN tunneling. Both of the source storage region and the drain storage region are programmed by channel hot electrons and erased by source-side or drain-side FN tunneling. The present invention can store three-bit data per cell, such that the storage density of the memory device can be substantially increased.Type: ApplicationFiled: April 30, 2010Publication date: August 25, 2011Applicant: ACER INCORPORATEDInventors: Ting-Chang CHANG, Fu-Yen JIAN, Shih-Ching CHEN, Te-Chih CHEN
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Patent number: 7983092Abstract: The present invention relates to a nonvolatile memory apparatus and a method of using a thin film transistor (TFT) as a nonvolatile memory by storing carriers in a body of the TFT, which operates a general TFT as a memory cell of a nonvolatile memory by manipulating the electrical characteristics of the TFT in order to integrate with other electrical components formed by TFTs, such as logic circuit or TFT-LCD pixel transistor, on the LCD panel without additional semiconductor manufacturing processes.Type: GrantFiled: May 13, 2009Date of Patent: July 19, 2011Assignee: Acer IncorporatedInventors: Ting-Chang Chang, Fu-Yen Jian, Te-Chih Chen
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Publication number: 20110103155Abstract: One embodiment of the present invention provides an operation method of a memory device. The memory device includes a source, a drain, and a channel region between the source and the drain, a gate dielectric with a charge storage layer on the channel region, and a gate on the gate dielectric, wherein the source, the drain and the channel region are located in a substrate. The operation method includes the following steps: applying a reverse bias between the gate and the drain of the memory device to generate band-to-band hot holes in the substrate near the drain; injecting the band-to-band hot holes to a drain side of the charge storage layer; and performing a program/erase operation upon the memory device. The band-to-band hot holes in the drain side of the charge storage layer are not completely vanished by the program/erase operation.Type: ApplicationFiled: July 22, 2010Publication date: May 5, 2011Applicant: ACER INCORPORATEDInventors: Ting-Chang Chang, Te-Chih Chen, Fu-Yen Jian, Chia-Sheng Lin
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Publication number: 20110096610Abstract: There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor.Type: ApplicationFiled: December 22, 2009Publication date: April 28, 2011Applicant: ACER INCORPORATEDInventors: Ting-Chang Chang, Shih-Ching Chen, Te-Chih Chen, Fu-Yen Jian, Yong-En Syu
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Publication number: 20100254185Abstract: The present invention relates to a nonvolatile memory apparatus and a method of using a thin film transistor (TFT) as a nonvolatile memory by storing carriers in a body of the TFT, which operates a general TFT as a memory cell of a nonvolatile memory by manipulating the electrical characteristics of the TFT in order to integrate with other electrical components formed by TFTs, such as logic circuit or TFT-LCD pixel transistor, on the LCD panel without additional semiconductor manufacturing processes.Type: ApplicationFiled: May 13, 2009Publication date: October 7, 2010Applicant: ACER INCORPORATEDInventors: Ting-Chang Chang, Fu-Yen Jian, Te-Chih Chen