Patents by Inventor Te-Chih WANG

Te-Chih WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967622
    Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Patent number: 11961893
    Abstract: Improved conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Publication number: 20240079409
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first fin structure. The semiconductor device structure includes a first source/drain structure over the first fin structure. The semiconductor device structure includes a first dielectric layer over the first source/drain structure and the substrate. The semiconductor device structure includes a first conductive contact structure in the first dielectric layer and over the first source/drain structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive contact structure. The semiconductor device structure includes a first conductive via structure passing through the second dielectric layer and connected to the first conductive contact structure. A first width direction of the first conductive contact structure is substantially parallel to a second width direction of the first conductive via structure.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jyun-De WU, Te-Chih HSIUNG, Yi-Chun CHANG, Yi-Chen WANG, Yuan-Tien TU, Peng WANG, Huan-Just LIN
  • Patent number: 9761003
    Abstract: A stereo image depth map generation device that includes a depth calculation module, a first order bilateral filter module and a second order bilateral filter module is provided. The depth calculation module receives a reference image including a plurality of reference pixels and a target image including a plurality of target pixels to generate an initial depth map according to pixel differences of the reference pixels and the target pixels. The first order bilateral filter module receives the initial depth map to perform a first order bilateral filtering calculation according to the initial depth map and the initial depth map itself to generate an averaged depth map. The second order bilateral filter module receives the averaged depth map and the target image to perform a second order bilateral filtering calculation according to the averaged depth map and the target image to generate a refined depth map.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: September 12, 2017
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Te-Chih Wang, Hao-Wei Peng, Chun-Te Wu, Chen-Yuan Luo
  • Publication number: 20170091946
    Abstract: A stereo image depth map generation device that includes a depth calculation module, a first order bilateral filter module and a second order bilateral filter module is provided. The depth calculation module receives a reference image including a plurality of reference pixels and a target image including a plurality of target pixels to generate an initial depth map according to pixel differences of the reference pixels and the target pixels. The first order bilateral filter module receives the initial depth map to perform a first order bilateral filtering calculation according to the initial depth map and the initial depth map itself to generate an averaged depth map. The second order bilateral filter module receives the averaged depth map and the target image to perform a second order bilateral filtering calculation according to the averaged depth map and the target image to generate a refined depth map.
    Type: Application
    Filed: May 3, 2016
    Publication date: March 30, 2017
    Inventors: Te-Chih WANG, Hao-Wei PENG, Chun-Te WU, Chen-Yuan LUO