Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.

Abstract: Improved conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first fin structure. The semiconductor device structure includes a first source/drain structure over the first fin structure. The semiconductor device structure includes a first dielectric layer over the first source/drain structure and the substrate. The semiconductor device structure includes a first conductive contact structure in the first dielectric layer and over the first source/drain structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive contact structure. The semiconductor device structure includes a first conductive via structure passing through the second dielectric layer and connected to the first conductive contact structure. A first width direction of the first conductive contact structure is substantially parallel to a second width direction of the first conductive via structure.

Abstract: The present invention provides methods of CMP polishing a metal surface, such as a copper or tungsten containing metal surface in a semiconductor wafer, the methods comprising CMP polishing the substrate with a CMP polishing pad that has a top polishing surface in a polishing layer which is the reaction product of an isocyanate terminated urethane prepolymer and a curative component comprising a polyol curative having a number average molecular weight of 6000 to 15,000, and having an average of 5 to 7 hydroxyl groups per molecule and a polyfunctional aromatic amine curative, wherein the polishing layer would if unfilled have a water uptake of 4 to 8 wt. % after one week of soaking in deionized (DI) water at room temperature. The methods form coplanar metal and dielectric or oxide layer surfaces with low defectivity and a minimized degree of dishing.

Abstract: The present invention provides methods of CMP polishing a metal surface, such as a copper or tungsten containing metal surface in a semiconductor wafer, the methods comprising CMP polishing the substrate with a CMP polishing pad that has a top polishing surface in a polishing layer which is the reaction product of an isocyanate terminated urethane prepolymer and a curative component comprising a polyol curative having a number average molecular weight of 6000 to 15,000, and having an average of 5 to 7 hydroxyl groups per molecule and a polyfunctional aromatic amine curative, wherein the polishing layer would if unfilled have a water to uptake of 4 to 8 wt. % after one week of soaking in deionized (DI) water at room temperature. The methods form coplanar metal and dielectric or oxide layer surfaces with low defectivity and a minimized degree of dishing.

Abstract: The present invention provides methods of CMP polishing a metal surface, such as a copper or tungsten containing metal surface in a semiconductor wafer, the methods comprising CMP polishing the substrate with a CMP polishing pad that has a top polishing surface in a polishing layer which is the reaction product of an isocyanate terminated urethane prepolymer and a curative component comprising a polyol curative having a number average molecular weight of 6000 to 15,000, and having an average of 5 to 7 hydroxyl groups per molecule and a polyfunctional aromatic amine curative, wherein the polishing layer would if unfilled have a water uptake of 4 to 8 wt. % after one week of soaking in deionized (DI) water at room temperature. The methods form coplanar metal and dielectric or oxide layer surfaces with low defectivity and a minimized degree of dishing.

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.

Abstract: A substrate having a blind hole and a method for forming the blind hole. The method includes: (a) providing a substrate having a lower dielectric layer, a copper layer, and an upper dielectric layer; and (b) forming an upper dielectric layer through hole and a copper layer through hole by etching through the upper dielectric layer and the copper layer with laser, and forming a cavity on the lower dielectric layer by using the laser, in which the aperture of the cavity on the upper surface of the lower dielectric layer is larger than that of the copper layer through hole. Therefore, a blind hole space in a shape of a rivet is formed, so that after the blind hole space is electroplated with an electroplating copper layer, the bonding force between the electroplating copper layer and the copper layer is enhanced.

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.

Abstract: A method for fabricating a conductive blind via of a circuit substrate including the following steps is provided. First, the circuit substrate including a first dielectric layer, a patterned circuit layer and a second dielectric layer are provided. The patterned circuit layer including at least a capture pad is disposed between the first dielectric layer and the second dielectric layer. Next, a blind via exposing the capture pad is formed in the second dielectric layer. Then, an electroless plating process is performed to form an electroless copper layer on the capture pad and an inner wall of the blind via. Next, the electroless copper layer on the capture pad is removed. Finally, the blind via is filled with a conductive material to form the conductive blind via.

Abstract: A phase change memory device comprising a substrate. A plurality of bottom electrodes isolated from each other is on the substrate. An insulating layer crosses a portion of the surfaces of any two of the adjacent bottom electrodes. A pair of phase change material spacers is on a pair of sidewalls of the insulating layer, wherein the pair of the phase change material spacers is on any two of the adjacent bottom electrodes, respectively. A top electrode is on the insulating layer and covers the phase change material spacers.

Abstract: A phase-change memory element is provided. The phase-change memory element of an embodiment of the invention comprises a phase-change material layer with a concave, and a heater with an extended part, wherein the extended part of the heater is wedged in the concave of the phase-change material layer. Specifically, the extended part of the heater has a length of 10˜5000 ?.

Abstract: A phase change memory device comprising a substrate. A plurality of bottom electrodes isolated from each other is on the substrate. An insulating layer crosses a portion of the surfaces of any two of the adjacent bottom electrodes. A pair of phase change material spacers is on a pair of sidewalls of the insulating layer, wherein the pair of the phase change material spacers is on any two of the adjacent bottom electrodes, respectively. A top electrode is on the insulating layer and covers the phase change material spacers.

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.

Abstract: The present invention relates to a substrate having a blind hole and a method for forming the blind hole. The method for forming the blind hole in the substrate includes: (a) providing a substrate having a lower dielectric layer, a copper layer, and an upper dielectric layer; and (b) forming an upper dielectric layer through hole and a copper layer through hole by etching through the upper dielectric layer and the copper layer with laser, and forming a cavity on the lower dielectric layer by using the laser, in which the aperture of the cavity on the upper surface of the lower dielectric layer is larger than that of the copper layer through hole. Therefore, a blind hole space in a shape of a rivet is formed, so that after the blind hole space is electroplated with an electroplating copper layer, the bonding force between the electroplating copper layer and the copper layer is enhanced.

Abstract: A method for fabricating a conductive blind via of a circuit substrate including the following steps is provided. First, the circuit substrate including a first dielectric layer, a patterned circuit layer and a second dielectric layer are provided. The patterned circuit layer including at least a capture pad is disposed between the first dielectric layer and the second dielectric layer. Next, a blind via exposing the capture pad is formed in the second dielectric layer. Then, an electroless plating process is performed to form an electroless copper layer on the capture pad and an inner wall of the blind via. Next, the electroless copper layer on the capture pad is removed. Finally, the blind via is filled with a conductive material to form the conductive blind via.