Patents by Inventor Te-Chun Wang
Te-Chun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10875144Abstract: The present invention provides methods of CMP polishing a metal surface, such as a copper or tungsten containing metal surface in a semiconductor wafer, the methods comprising CMP polishing the substrate with a CMP polishing pad that has a top polishing surface in a polishing layer which is the reaction product of an isocyanate terminated urethane prepolymer and a curative component comprising a polyol curative having a number average molecular weight of 6000 to 15,000, and having an average of 5 to 7 hydroxyl groups per molecule and a polyfunctional aromatic amine curative, wherein the polishing layer would if unfilled have a water uptake of 4 to 8 wt. % after one week of soaking in deionized (DI) water at room temperature. The methods form coplanar metal and dielectric or oxide layer surfaces with low defectivity and a minimized degree of dishing.Type: GrantFiled: August 8, 2018Date of Patent: December 29, 2020Assignee: ROHM AND HAAS ELECTRONIC MATERIALS CMP HOLDINGS, IInventors: Bainian Qian, Fengji Yeh, Te-Chun Wang, Sheng-Huan Tseng, Kevin Wen-Huan Tung, Marty W. DeGroot
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Publication number: 20180361531Abstract: The present invention provides methods of CMP polishing a metal surface, such as a copper or tungsten containing metal surface in a semiconductor wafer, the methods comprising CMP polishing the substrate with a CMP polishing pad that has a top polishing surface in a polishing layer which is the reaction product of an isocyanate terminated urethane prepolymer and a curative component comprising a polyol curative having a number average molecular weight of 6000 to 15,000, and having an average of 5 to 7 hydroxyl groups per molecule and a polyfunctional aromatic amine curative, wherein the polishing layer would if unfilled have a water to uptake of 4 to 8 wt. % after one week of soaking in deionized (DI) water at room temperature. The methods form coplanar metal and dielectric or oxide layer surfaces with low defectivity and a minimized degree of dishing.Type: ApplicationFiled: August 8, 2018Publication date: December 20, 2018Inventors: Bainian Qian, Fengji Yeh, Te-Chun Wang, Sheng-Huan Tseng, Kevin Wen-Huan Tung, Marty W. DeGroot
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Publication number: 20180281149Abstract: The present invention provides methods of CMP polishing a metal surface, such as a copper or tungsten containing metal surface in a semiconductor wafer, the methods comprising CMP polishing the substrate with a CMP polishing pad that has a top polishing surface in a polishing layer which is the reaction product of an isocyanate terminated urethane prepolymer and a curative component comprising a polyol curative having a number average molecular weight of 6000 to 15,000, and having an average of 5 to 7 hydroxyl groups per molecule and a polyfunctional aromatic amine curative, wherein the polishing layer would if unfilled have a water uptake of 4 to 8 wt. % after one week of soaking in deionized (DI) water at room temperature. The methods form coplanar metal and dielectric or oxide layer surfaces with low defectivity and a minimized degree of dishing.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Bainian Qian, Fengji Yeh, Te-Chun Wang, Sheng-Huan Tseng, Kevin Wen-Huan Tung, Marty W. DeGroot
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Patent number: 8242034Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.Type: GrantFiled: November 5, 2010Date of Patent: August 14, 2012Assignee: Powerchip Technology CorporationInventors: Yung-Fa Lin, Te-Chun Wang
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Patent number: 7927499Abstract: A substrate having a blind hole and a method for forming the blind hole. The method includes: (a) providing a substrate having a lower dielectric layer, a copper layer, and an upper dielectric layer; and (b) forming an upper dielectric layer through hole and a copper layer through hole by etching through the upper dielectric layer and the copper layer with laser, and forming a cavity on the lower dielectric layer by using the laser, in which the aperture of the cavity on the upper surface of the lower dielectric layer is larger than that of the copper layer through hole. Therefore, a blind hole space in a shape of a rivet is formed, so that after the blind hole space is electroplated with an electroplating copper layer, the bonding force between the electroplating copper layer and the copper layer is enhanced.Type: GrantFiled: August 10, 2007Date of Patent: April 19, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Te-Chun Wang
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Publication number: 20110053333Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.Type: ApplicationFiled: November 5, 2010Publication date: March 3, 2011Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Yung-Fa Lin, Te-Chun Wang
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Patent number: 7855378Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.Type: GrantFiled: August 8, 2007Date of Patent: December 21, 2010Assignee: Powerchip Semiconductor Crop.Inventors: Yung-Fa Lin, Te-Chun Wang
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Patent number: 7698813Abstract: A method for fabricating a conductive blind via of a circuit substrate including the following steps is provided. First, the circuit substrate including a first dielectric layer, a patterned circuit layer and a second dielectric layer are provided. The patterned circuit layer including at least a capture pad is disposed between the first dielectric layer and the second dielectric layer. Next, a blind via exposing the capture pad is formed in the second dielectric layer. Then, an electroless plating process is performed to form an electroless copper layer on the capture pad and an inner wall of the blind via. Next, the electroless copper layer on the capture pad is removed. Finally, the blind via is filled with a conductive material to form the conductive blind via.Type: GrantFiled: December 21, 2006Date of Patent: April 20, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Te-Chun Wang
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Patent number: 7655941Abstract: A phase change memory device comprising a substrate. A plurality of bottom electrodes isolated from each other is on the substrate. An insulating layer crosses a portion of the surfaces of any two of the adjacent bottom electrodes. A pair of phase change material spacers is on a pair of sidewalls of the insulating layer, wherein the pair of the phase change material spacers is on any two of the adjacent bottom electrodes, respectively. A top electrode is on the insulating layer and covers the phase change material spacers.Type: GrantFiled: November 15, 2007Date of Patent: February 2, 2010Assignees: Industrial Technology Research Institute, Powerchip Semiconductor Corp., Nanya Technology Corporation, ProMOS Technologies, Inc., Winbond Electronics Corp.Inventors: Yung-Fa Lin, Te-Chun Wang
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Publication number: 20090008621Abstract: A phase-change memory element is provided. The phase-change memory element of an embodiment of the invention comprises a phase-change material layer with a concave, and a heater with an extended part, wherein the extended part of the heater is wedged in the concave of the phase-change material layer. Specifically, the extended part of the heater has a length of 10˜5000 ?.Type: ApplicationFiled: December 28, 2007Publication date: January 8, 2009Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, POWERCHIP SEMICONDUCTOR CORP., NANYA TECHNOLOGY CORPORATION, PROMOS TECHNOLOGIES INC., WINBOND ELECTRONICS CORP.Inventors: Yung-Fa Lin, Te-Chun Wang
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Publication number: 20080290335Abstract: A phase change memory device comprising a substrate. A plurality of bottom electrodes isolated from each other is on the substrate. An insulating layer crosses a portion of the surfaces of any two of the adjacent bottom electrodes. A pair of phase change material spacers is on a pair of sidewalls of the insulating layer, wherein the pair of the phase change material spacers is on any two of the adjacent bottom electrodes, respectively. A top electrode is on the insulating layer and covers the phase change material spacers.Type: ApplicationFiled: November 15, 2007Publication date: November 27, 2008Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, POWERCHIP SEMICONDUCTOR CORP., NANYA TECHNOLOGY CORPORATION, PROMOS TECHNOLOGIES INC., WINBOND ELECTRONICS CORP.Inventors: Yung-Fa Lin, Te-Chun Wang
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Publication number: 20080272358Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.Type: ApplicationFiled: August 8, 2007Publication date: November 6, 2008Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, POWERCHIP SEMICONDUCTOR CORP., NANYA TECHNOLOGY CORPORATION, PROMOS TECHNOLOGIES INC., WINBOND ELECTRONICS CORP.Inventors: Yung-Fa Lin, Te-Chun Wang
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Publication number: 20080041822Abstract: The present invention relates to a substrate having a blind hole and a method for forming the blind hole. The method for forming the blind hole in the substrate includes: (a) providing a substrate having a lower dielectric layer, a copper layer, and an upper dielectric layer; and (b) forming an upper dielectric layer through hole and a copper layer through hole by etching through the upper dielectric layer and the copper layer with laser, and forming a cavity on the lower dielectric layer by using the laser, in which the aperture of the cavity on the upper surface of the lower dielectric layer is larger than that of the copper layer through hole. Therefore, a blind hole space in a shape of a rivet is formed, so that after the blind hole space is electroplated with an electroplating copper layer, the bonding force between the electroplating copper layer and the copper layer is enhanced.Type: ApplicationFiled: August 10, 2007Publication date: February 21, 2008Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Te-Chun Wang
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Publication number: 20070163112Abstract: A method for fabricating a conductive blind via of a circuit substrate including the following steps is provided. First, the circuit substrate including a first dielectric layer, a patterned circuit layer and a second dielectric layer are provided. The patterned circuit layer including at least a capture pad is disposed between the first dielectric layer and the second dielectric layer. Next, a blind via exposing the capture pad is formed in the second dielectric layer. Then, an electroless plating process is performed to form an electroless copper layer on the capture pad and an inner wall of the blind via. Next, the electroless copper layer on the capture pad is removed. Finally, the blind via is filled with a conductive material to form the conductive blind via.Type: ApplicationFiled: December 21, 2006Publication date: July 19, 2007Inventor: Te-Chun Wang