Patents by Inventor Te-En CHENG
Te-En CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250176204Abstract: A method of forming a semiconductor device includes forming a sacrificial layer over a first stack of nanostructures and an isolation region. A dummy gate structure is formed over the first stack of nanostructures, and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure. A spacer layer is formed over the dummy gate structure. A first portion of the spacer layer physically contacts the first stack of nanostructures.Type: ApplicationFiled: January 27, 2025Publication date: May 29, 2025Inventors: Te-En Cheng, Yung-Cheng Lu, Chi On Chui, Wei-Yang Lee
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Patent number: 12237399Abstract: A method of forming a semiconductor device includes forming a sacrificial layer over a first stack of nanostructures and an isolation region. A dummy gate structure is formed over the first stack of nanostructures, and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure. A spacer layer is formed over the dummy gate structure. A first portion of the spacer layer physically contacts the first stack of nanostructures.Type: GrantFiled: August 27, 2021Date of Patent: February 25, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Te-En Cheng, Yung-Cheng Lu, Chi On Chui, Wei-Yang Lee
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Publication number: 20240395898Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a source epitaxial structure, a drain epitaxial structure, a first gate spacer, and a second gate spacer. The semiconductor fin is over a substrate. The gate structure extends across the semiconductor fin. The source epitaxial structure and the drain epitaxial structure are on opposite sides of the gate structure, respectively. The first gate spacer separates the source epitaxial structure from the gate structure. The second gate spacer separates the drain epitaxial structure from the gate structure. The first and second gate spacers are made of an organosilicate glass material having a dielectric constant greater than a dielectric constant of silicon oxide.Type: ApplicationFiled: July 30, 2024Publication date: November 28, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-En CHENG, Yung-Cheng LU, Chi On CHUI
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Patent number: 12107145Abstract: A method includes following steps. Fins are formed over a substrate. A dummy gate structure is across the fins. A spacer layer is deposited over the dummy gate structure. The spacer layer has a first portion in a void of the dummy gate structure and a second portion outside the void of the dummy gate structure. The second portion of the spacer layer is treated to have a different material composition than the first portion of the spacer layer, and is then etched to form gate spacers on sidewalls of the dummy gate structure. An etching process is performed on the dummy gate structure to form a gate trench between the gate spacers. The etching process etches the first portion of the spacer layer at a faster etch rate than etching the gate spacers. A gate structure is formed in the gate trench.Type: GrantFiled: July 7, 2021Date of Patent: October 1, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-En Cheng, Yung-Cheng Lu, Chi On Chui
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Publication number: 20240258100Abstract: Fabrication of semiconductor devices is provided. A chamber is evacuated to a pressure of less than about 1 Torr. The chamber is heated to a temperature in excess of about 400° C. A precursor is introduced into the chamber. The precursor is decomposed with a first plasma. A first layer is deposited on a surface of the semiconductor device based on the decomposed precursor. The precursor is densified to form a first gate spacer. The precursor is introduced into the chamber subsequent to forming the first layer. The precursor is decomposed with a second plasma. A second layer is deposited on the surface of the semiconductor device based on the decomposed precursor. The deposited precursor is densified to form a second gate spacer.Type: ApplicationFiled: January 30, 2023Publication date: August 1, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Ling Liao, Te-En Cheng, Nai-Yu Yeh, Ming-Han Chung, Chunyao Wang, Yung-Cheng LU
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Publication number: 20230326746Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer.Type: ApplicationFiled: May 31, 2023Publication date: October 12, 2023Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
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Patent number: 11705327Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.Type: GrantFiled: April 4, 2022Date of Patent: July 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
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Publication number: 20230064457Abstract: A method of forming a semiconductor device includes forming a sacrificial layer over a first stack of nanostructures and an isolation region. A dummy gate structure is formed over the first stack of nanostructures, and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure. A spacer layer is formed over the dummy gate structure. A first portion of the spacer layer physically contacts the first stack of nanostructures.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Te-En Cheng, Yung-Chen Lu, Chi On Chui, Wei-Yang Lee
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Publication number: 20230045665Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a fin structure that protrudes above a substrate, where the fin structure includes a fin and a layer stack over the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings exposes first portions of the first semiconductor material and second portions of the second semiconductor material; recessing the exposed first portions of the first semiconductor material to form sidewall recesses in the first semiconductor material; lining the sidewall recesses with a first dielectric material; depositing a second dielectric material in the sidewall recesses on the first dielectric material; after depositing the second dielectric material, annealing the second dielectric material; and after the annealing, forming source/drain regions in the openings.Type: ApplicationFiled: February 7, 2022Publication date: February 9, 2023Inventors: Wen-Kai Lin, Te-En Cheng, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu
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Publication number: 20220336626Abstract: A method includes following steps. Fins are formed over a substrate. A dummy gate structure is across the fins. A spacer layer is deposited over the dummy gate structure. The spacer layer has a first portion in a void of the dummy gate structure and a second portion outside the void of the dummy gate structure. The second portion of the spacer layer is treated to have a different material composition than the first portion of the spacer layer, and is then etched to form gate spacers on sidewalls of the dummy gate structure. An etching process is performed on the dummy gate structure to form a gate trench between the gate spacers. The etching process etches the first portion of the spacer layer at a faster etch rate than etching the gate spacers. A gate structure is formed in the gate trench.Type: ApplicationFiled: July 7, 2021Publication date: October 20, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-En CHENG, Yung-Cheng LU, Chi On CHUI
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Publication number: 20220230871Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.Type: ApplicationFiled: April 4, 2022Publication date: July 21, 2022Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
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Patent number: 11295948Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.Type: GrantFiled: March 15, 2021Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
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Patent number: 11205597Abstract: A method includes forming a first fin extending from a substrate, forming a first gate stack over and along sidewalls of the first fin, forming a first spacer along a sidewall of the first gate stack, the first spacer including a first composition of silicon oxycarbide, forming a second spacer along a sidewall of the first spacer, the second spacer including a second composition of silicon oxycarbide, forming a third spacer along a sidewall of the second spacer, the third spacer including silicon nitride, and forming a first epitaxial source/drain region in the first fin and adjacent the third spacer.Type: GrantFiled: July 1, 2019Date of Patent: December 21, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chun Tan, I-Hsieh Wong, Te-En Cheng, Yung-Hui Lin, Wei-Ken Lin, Wei-Yang Lee, Chih-Hung Nien
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Publication number: 20210202235Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.Type: ApplicationFiled: March 15, 2021Publication date: July 1, 2021Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
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Patent number: 10950431Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.Type: GrantFiled: May 24, 2019Date of Patent: March 16, 2021Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
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Patent number: 10847634Abstract: Field effect transistor and methods of forming the same are disclosed. The field effect transistor includes a gate electrode, a contact etch stop layer (CESL), an inter layer dielectric (ILD) and a protection layer. The CESL includes SiCON and is disposed on a sidewall of the gate electrode. The IDL is laterally adjacent to the gate electrode. The protection layer covers the CESL and is disposed between the CESL and the ILD.Type: GrantFiled: January 31, 2018Date of Patent: November 24, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Te-En Cheng, Chun-Te Li, Kai-Hsuan Lee, Tien-I Bao, Wei-Ken Lin
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Publication number: 20200105620Abstract: A method includes forming a first fin extending from a substrate, forming a first gate stack over and along sidewalls of the first fin, forming a first spacer along a sidewall of the first gate stack, the first spacer including a first composition of silicon oxycarbide, forming a second spacer along a sidewall of the first spacer, the second spacer including a second composition of silicon oxycarbide, forming a third spacer along a sidewall of the second spacer, the third spacer including silicon nitride, and forming a first epitaxial source/drain region in the first fin and adjacent the third spacer.Type: ApplicationFiled: July 1, 2019Publication date: April 2, 2020Inventors: Wei-Chun Tan, I-Hsieh Wong, Te-En Cheng, Yung-Hui Lin, Wei-Ken Lin, Wei-Yang Lee, Chih-Hung Nien
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Publication number: 20190279863Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.Type: ApplicationFiled: May 24, 2019Publication date: September 12, 2019Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
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Patent number: 10304677Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.Type: GrantFiled: April 13, 2018Date of Patent: May 28, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
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Publication number: 20190131436Abstract: Field effect transistor and methods of forming the same are disclosed. The field effect transistor includes a gate electrode, a contact etch stop layer (CESL), an inter layer dielectric (ILD) and a protection layer. The CESL includes SiCON and is disposed on a sidewall of the gate electrode. The IDL is laterally adjacent to the gate electrode. The protection layer covers the CESL and is disposed between the CESL and the ILD.Type: ApplicationFiled: January 31, 2018Publication date: May 2, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Te-En Cheng, Chun-Te Li, Kai-Hsuan Lee, Tien-I Bao, Wei-Ken Lin