Patents by Inventor Te-Fang Chu
Te-Fang Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11527472Abstract: A supporting structure is provided, which forms a protective layer on a metal member having a plurality of conductive posts, and the protective layer is exposed from end surfaces of the conductive posts, such that conductors are formed on the end surfaces of the conductive posts, thereby avoiding damage of the protective layer.Type: GrantFiled: May 6, 2020Date of Patent: December 13, 2022Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Cho-Hsin Chang, Hao-Ju Fang, Ting-Wei Chi, Te-Fang Chu
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Publication number: 20210305148Abstract: A supporting structure is provided, which forms a protective layer on a metal member having a plurality of conductive posts, and the protective layer is exposed from end surfaces of the conductive posts, such that conductors are formed on the end surfaces of the conductive posts, thereby avoiding damage of the protective layer.Type: ApplicationFiled: May 6, 2020Publication date: September 30, 2021Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Cho-Hsin Chang, Hao-Ju Fang, Ting-Wei Chi, Te-Fang Chu
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Patent number: 10566320Abstract: An electronic package is provided, including: a substrate having opposite first and second surfaces; at least a first electronic element disposed on the first surface of the substrate; a first encapsulant encapsulating the first electronic element; at least a second electronic element and a frame disposed on the second surface of the substrate; and a second encapsulant encapsulating the second electronic element. By disposing the first and second electronic elements on the first and second surfaces of the substrate, respectively, the invention allows a required number of electronic elements to be mounted on the substrate without the need to increase the surface area of the substrate. Since the volume of the electronic package does not increase, the electronic package meets the miniaturization requirement. The present invention further provides a method for fabricating the electronic package.Type: GrantFiled: December 6, 2018Date of Patent: February 18, 2020Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chi-Liang Shih, Chun-Chong Chien, Hsin-Lung Chung, Te-Fang Chu
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Publication number: 20190115330Abstract: An electronic package is provided, including: a substrate having opposite first and second surfaces; at least a first electronic element disposed on the first surface of the substrate; a first encapsulant encapsulating the first electronic element; at least a second electronic element and a frame disposed on the second surface of the substrate; and a second encapsulant encapsulating the second electronic element. By disposing the first and second electronic elements on the first and second surfaces of the substrate, respectively, the invention allows a required number of electronic elements to be mounted on the substrate without the need to increase the surface area of the substrate. Since the volume of the electronic package does not increase, the electronic package meets the miniaturization requirement. The present invention further provides a method for fabricating the electronic package.Type: ApplicationFiled: December 6, 2018Publication date: April 18, 2019Inventors: Chi-Liang Shih, Chun-Chong Chien, Hsin-Lung Chung, Te-Fang Chu
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Patent number: 10181458Abstract: An electronic package is provided, including: a substrate having opposite first and second surfaces; at least a first electronic element disposed on the first surface of the substrate; a first encapsulant encapsulating the first electronic element; at least a second electronic element and a frame disposed on the second surface of the substrate; and a second encapsulant encapsulating the second electronic element. By disposing the first and second electronic elements on the first and second surfaces of the substrate, respectively, the invention allows a required number of electronic elements to be mounted on the substrate without the need to increase the surface area of the substrate. Since the volume of the electronic package does not increase, the electronic package meets the miniaturization requirement. The present invention further provides a method for fabricating the electronic package.Type: GrantFiled: December 28, 2015Date of Patent: January 15, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chi-Liang Shih, Chun-Chong Chien, Hsin-Lung Chun, Te-Fang Chu
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Publication number: 20170040304Abstract: An electronic package is provided, including: a substrate having opposite first and second surfaces; at least a first electronic element disposed on the first surface of the substrate; a first encapsulant encapsulating the first electronic element; at least a second electronic element and a frame disposed on the second surface of the substrate; and a second encapsulant encapsulating the second electronic element. By disposing the first and second electronic elements on the first and second surfaces of the substrate, respectively, the invention allows a required number of electronic elements to be mounted on the substrate without the need to increase the surface area of the substrate. Since the volume of the electronic package does not increase, the electronic package meets the miniaturization requirement. The present invention further provides a method for fabricating the electronic package.Type: ApplicationFiled: December 28, 2015Publication date: February 9, 2017Inventors: Chi-Liang Shih, Chun-Chong Chien, Hsin-Lung Chun, Te-Fang Chu
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Patent number: 9526171Abstract: A package structure is provided, which includes: a substrate having opposite first and second surfaces; at least an electronic element disposed on the first surface of the substrate; and an encapsulant formed on the first surface of the substrate for encapsulating the electronic element. The encapsulant has a non-rectangular shape so as to reduce an ineffective space in the encapsulant.Type: GrantFiled: December 9, 2014Date of Patent: December 20, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chi-Liang Shih, Hsin-Lung Chung, Te-Fang Chu, Hao-Ju Fang, Kuang-Neng Chung
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Patent number: 9490219Abstract: This invention provides a semiconductor package, including a substrate, a plurality of semiconductor elements disposed on the substrate, at least one shielding member disposed between at least two of the semiconductor elements, and an encapsulant encapsulating the semiconductor elements and shielding members. Through the shielding member, electromagnetic interference caused among semiconductor elements can be prevented.Type: GrantFiled: August 14, 2014Date of Patent: November 8, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Cho-Hsin Chang, Tsung-Hsien Hsu, Hsin-Lung Chung, Te-Fang Chu, Chia-Yang Chen
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Patent number: 9343401Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a packaging substrate having a first surface with a plurality of bonding pads and an opposite second surface; disposing a plurality of passive elements on the first surface of the packaging substrate; disposing a semiconductor chip on the passive elements through an adhesive film; electrically connecting the semiconductor chip and the bonding pads through a plurality of bonding wires; and forming an encapsulant on the first surface of the packaging substrate for encapsulating the semiconductor chip, the passive elements and the bonding wires. By disposing the passive elements between the packaging substrate and the semiconductor chip, the invention saves space on the packaging substrate and increases the wiring flexibility. Further, since the bonding wires are not easy to come into contact with the passive elements, the invention prevents a short circuit from occurring.Type: GrantFiled: April 18, 2014Date of Patent: May 17, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chi-Liang Shih, Hsin-Lung Chung, Te-Fang Chu, Sheng-Ming Yang, Hung-Cheng Chen, Chia-Yang Chen
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Publication number: 20150366085Abstract: A package structure is provided, which includes: a substrate having opposite first and second surfaces; at least an electronic element disposed on the first surface of the substrate; and an encapsulant formed on the first surface of the substrate for encapsulating the electronic element. The encapsulant has a non-rectangular shape so as to reduce an ineffective space in the encapsulant.Type: ApplicationFiled: December 9, 2014Publication date: December 17, 2015Inventors: Chi-Liang Shih, Hsin-Lung Chung, Te-Fang Chu, Hao-Ju Fang, Kuang-Neng Chung
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Publication number: 20150333017Abstract: This invention provides a semiconductor package, including a substrate, a plurality of semiconductor elements disposed on the substrate, at least one shielding member disposed between at least two of the semiconductor elements, and an encapsulant encapsulating the semiconductor elements and shielding members. Through the shielding member, electromagnetic interference caused among semiconductor elements can be prevented.Type: ApplicationFiled: August 14, 2014Publication date: November 19, 2015Inventors: Cho-Hsin Chang, Tsung-Hsien Hsu, Hsin-Lung Chung, Te-Fang Chu, Chia-Yang Chen
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Publication number: 20150243574Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a packaging substrate having a first surface with a plurality of bonding pads and an opposite second surface; disposing a plurality of passive elements on the first surface of the packaging substrate; disposing a semiconductor chip on the passive elements through an adhesive film; electrically connecting the semiconductor chip and the bonding pads through a plurality of bonding wires; and forming an encapsulant on the first surface of the packaging substrate for encapsulating the semiconductor chip, the passive elements and the bonding wires. By disposing the passive elements between the packaging substrate and the semiconductor chip, the invention saves space on the packaging substrate and increases the wiring flexibility. Further, since the bonding wires are not easy to come into contact with the passive elements, the invention prevents a short circuit from occurring.Type: ApplicationFiled: April 18, 2014Publication date: August 27, 2015Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Chi-Liang Shih, Hsin-Lung Chung, Te-Fang Chu, Sheng-Ming Yang, Hung-Cheng Chen, Chia-Yang Chen
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Publication number: 20140264958Abstract: A semiconductor package is disclosed, which includes: a substrate body; a semiconductor element disposed on the substrate body; and a molding compound forms on the substrate body for encapsulating the semiconductor element. The molding compound contains a metal oxide so as to have a high insulation impedance and a high heat dissipating rate and be capable of suppressing electromagnetic interference.Type: ApplicationFiled: August 16, 2013Publication date: September 18, 2014Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Tsung-Hsien Hsu, Hsin-Lung Chung, Te-Fang Chu, Kwok-Yan Lam, Shao-Meng Sim
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Publication number: 20140203771Abstract: An electronic package is provided, which includes: a substrate, a charging module and a coil module disposed on the substrate, and an encapsulant formed on the substrate for encapsulating the charging module and the coil module. The coil module has a plurality of coils having an opening, an adhesive compound formed on the coils in a manner that the opening of the coils is exposed from the adhesive compound, and a magnet inserted in the opening of the coils. Further, the adhesive compound comprises a metal oxide. Compared with the conventional ferrite, the adhesive compound is flexible and not easy to crack or break during transportation or assembly, thereby greatly improving the charging efficiency of the electronic package.Type: ApplicationFiled: August 6, 2013Publication date: July 24, 2014Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Tsung-Hsien Hsu, Hsin-Lung Chung, Te-Fang Chu, Chia-Yang Chen, Kwok-Yan Lam
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Publication number: 20090251878Abstract: An electronic assembly includes: a circuit substrate with a first mounting surface that has a plurality of spaced apart first mounting regions and at least one second mounting region spaced apart from the first mounting regions; a plurality of first electronic components mounted on the first mounting regions, respectively; and at least one dummy of a non-electronic component mounted on the second mounting region and having dimensions simulating those of the first electronic components. A method for making electronic devices is also disclosed.Type: ApplicationFiled: April 2, 2008Publication date: October 8, 2009Inventors: Tsung-Hsien Hsu, Te-Fang Chu, Hsing-Lung Chung