Abstract: One or more embodiments of the present description provide a method and device for risk prediction of thermal runaway in LIB. The method includes: acquiring knowledge of a mechanism for thermal runaway in LIB; describing an evolution process of thermal runaway in LIB by adopting a fault tree; mapping a fault tree structure to a dynamic Bayesian network model for thermal runaway in LIB to obtain quantitative results of a risk of thermal runaway in LIB; and taking the quantitative results of a dynamic Bayesian network as inputs of a machine learning model to obtain prediction results of the risk of thermal runaway. By using the method in the present embodiment, an evolution trend of battery thermal runaway can be predicted by fusing multiple thermal runaway causes and multi-source data, and thus, the prediction results are relatively accurate.

Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Abstract: An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-? dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-?) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one ?m2. Polysilicon gates with these adaptations may be operative with gate voltages of 10 V or higher and may be used in embedded memory devices.

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region.

Abstract: The present disclosure provides a semiconductor device, including a substrate, a first active region in the substrate, a second active region in the substrate and adjacent to the first active region, an isolation region in the substrate and between the first active region and the second active region, and a dummy gate overlapping with the isolation region, wherein an entire bottom width of the dummy gate is greater than an entire top width of the isolation region.

Abstract: In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.

Abstract: The present disclosure relates to a method for providing biomarker for early detection of Alzheimer's Disease (AD), and particularly to a method that is able to enhance the accuracy of predicting AD from Mild Cognitive Impairment (MCI) patients using the Hippocampus magnetic resonance imaging (MRI) scans and Mini-Mental State Examination (MMSE) data. The providing MRI images containing the anatomical structure of Hippocampus biomarker and MMSE data as a training data set; training a processor using the training data set, and the training comprising acts of receiving MRI images and MMSE data as a testing data set from a target; and classifying the test data by the trained processor to include aggregating predictions.

Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.

Abstract: The present disclosure relates to a method for providing biomarker for early detection of Alzheimer's Disease (AD), and particularly to a method that is able to enhance the accuracy of predicting AD from Mild Cognitive Impairment (MCI) patients using the Hippocampus magnetic resonance imaging (MRI) scans and Mini-Mental State Examination (MMSE) data. The providing MRI images containing the anatomical structure of Hippocampus biomarker and MMSE data as a training data set; training a processor using the training data set, and the training comprising acts of receiving MRI images and MMSE data as a testing data set from a target; and classifying the test data by the trained processor to include aggregating predictions.

Abstract: The present disclosure relates to a method for providing biomarker for early detection of Alzheimer's Disease (AD), and particularly to a method that is able to enhance the accuracy of predicting AD from Mild Cognitive Impairment (MCI) patients using the Hippocampus magnetic resonance imaging (MRI) scans and Mini-Mental State Examination (MMSE) data. The providing MRI images containing the anatomical structure of Hippocampus biomarker and MMSE data as a training data set; training a processor using the training data set, and the training comprising acts of receiving MRI images and MMSE data as a testing data set from a target; and classifying the test data by the trained processor to include aggregating predictions.

Abstract: A method for arranging a current source array of a DAC and a layout of a common-source current source array are provided in embodiments of the present disclosure for improving linearity and related performance of the DAC. The method includes, determining a number R of rows and a number C of columns of a common-source current source array; dividing the common-source current source array into M sub-arrays; segmenting the DAC to obtain (2X?1) groups of thermometer encoding current sources and Y groups of binary encoding current sources; arranging the (2X?1) groups of the thermometer encoding current sources into the M sub-arrays, arranging Y groups of binary encoding current sources into the M sub-arrays based on a number of binary encoding current sources in each of Y groups; arranging bias current sources evenly into the common-source current source array; and arranging other current sources as dummy cells.

Abstract: An RC oscillator is provided for improving stability of oscillation frequency. The circuit includes an input module, an oscillating module, an inverting module, first and second compensating modules and an output module, wherein the input module provides two-path charging currents and bias current for the oscillating module; the oscillating module outputs a first high level or a first low level to the inverting module under the control of the two-path charging currents and bias current, and improves frequency tuning accuracy of the oscillator; the inverting module inverts the first high level to a second low level or inverts the first low level to a second high level, and outputs the second low level or the second high level to the output module; the output module outputs the second high level and the second low level; and the first and second compensating modules improve stability of the oscillation frequency.

Abstract: A method for arranging a current source array of a DAC and a layout of a common-source current source array are provided in embodiments of the present disclosure for improving linearity and related performance of the DAC. The method includes, determining a number R of rows and a number C of columns of a common-source current source array; dividing the common-source current source array into M sub-arrays; segmenting the DAC to obtain (2X?1) groups of thermometer encoding current sources and Y groups of binary encoding current sources; arranging the (2X?1) groups of the thermometer encoding current sources into the M sub-arrays; arranging Y groups of binary encoding current sources into the M sub-arrays based on a number of binary encoding current sources in each of Y groups; arranging bias current sources evenly into the common-source current source array; and arranging other current sources as dummy cells.

Abstract: An RC oscillator is provided for improving stability of oscillation frequency. The circuit includes an input module, an oscillating module, an inverting module, first and second compensating modules and an output module, wherein the input module provides two-path charging currents and bias current for the oscillating module; the oscillating module outputs a first high level or a first low level to the inverting module under the control of the two-path charging currents and bias current, and improves frequency tuning accuracy of the oscillator; the inverting module inverts the first high level to a second low level or inverts the first low level to a second high level, and outputs the second low level or the second high level to the output module; the output module outputs the second high level and the second low level; and the first and second compensating modules improve stability of the oscillation frequency.