Patents by Inventor Te-Hsun Fu

Te-Hsun Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10776558
    Abstract: A testing method includes the following operations: performing a place and route procedure according to a netlist file corresponding to a chip to generate first layout data; determining whether to replace a flip-flop circuit in the chip with a gated flip-flop circuit according to the first layout data to generate second layout data; and running a test on the chip according to the second layout data.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: September 15, 2020
    Assignee: Global Unichip (Nanjing) Ltd.
    Inventors: Shih-Hsin Chen, Te-Hsun Fu, Ming-Tung Chang
  • Publication number: 20200151299
    Abstract: A testing method includes the following operations: performing a place and route procedure according to a netlist file corresponding to a chip, in order to generate first layout data; determining whether to replace a flip-flop circuit in the chip with a gated flip-flop circuit according to the first layout data, in order to generate second layout data; and running a test on the chip according to the second layout data.
    Type: Application
    Filed: March 21, 2019
    Publication date: May 14, 2020
    Inventors: Shih-Hsin Chen, Te-Hsun Fu, Ming-Tung Chang
  • Patent number: 9710580
    Abstract: A timing analysis method for a digital circuit design, a system and a computer readable storage media thereof are provided. The timing analysis method includes following steps. An integrated circuit (IC) design is obtained, wherein the IC is operated in a plurality of operating modes. A plurality of extracted timing models (ETMs) are respectively generated according to the operating modes of the IC design, wherein each of the ETMs includes a none on-chip variation (NOCV) part and an on-chip variation (OCV) part. The ETMs corresponding to the operating modes are integrated into a NOCV ETM and an OCV ETM, wherein the OCV part of the operating modes is not considered when the NOCV ETM is generated. And, a timing checking of the IC design is analyzed according to the NOCV ETM and the OCV ETM.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: July 18, 2017
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Teng-Nan Liao, Te-Hsun Fu, Hsin-Hsiung Liao, Cheng-Hong Tsai, Min-Hsiu Tsai
  • Publication number: 20170011161
    Abstract: A timing analysis method for a digital circuit design, a system and a computer readable storage media thereof are provided. The timing analysis method includes following steps. An integrated circuit (IC) design is obtained, wherein the IC is operated in a plurality of operating modes. A plurality of extracted timing models (ETMs) are respectively generated according to the operating modes of the IC design, wherein each of the ETMs includes a none on-chip variation (NOCV) part and an on-chip variation (OCV) part. The ETMs corresponding to the operating modes are integrated into a NOCV ETM and an OCV ETM, wherein the OCV part of the operating modes is not considered when the NOCV ETM is generated. And, a timing checking of the IC design is analyzed according to the NOCV ETM and the OCV ETM.
    Type: Application
    Filed: July 6, 2015
    Publication date: January 12, 2017
    Inventors: Teng-Nan Liao, Te-Hsun Fu, Hsin-Hsiung Liao, Cheng-Hong Tsai, Min-Hsiu Tsai