Patents by Inventor Te-Hsun Lin
Te-Hsun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153860Abstract: An electronic device is provided. The electronic device includes a redistribution structure, an electronic unit and a first conductive pad. The first conductive pad is disposed between the redistribution structure and the electronic unit. The electronic unit is electrically connected to the redistribution structure through the first conductive pad. The first conductive pad has a first coefficient of thermal expansion and a first Young's modulus. The first coefficient of thermal expansion and the first Young's modulus conform to the following formula: 0.7×(0.0069E2?1.1498E+59.661)?CTE?1.3×(0.0069E2?1.1498E+59.661), wherein CTE is the first coefficient of thermal expansion, and E is the first Young's modulus in the formula.Type: ApplicationFiled: December 21, 2022Publication date: May 9, 2024Inventors: Te-Hsun LIN, Wen-Hsiang LIAO, Yung-Feng CHEN, Ming-Hsien SHIH
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Publication number: 20240145370Abstract: A semiconductor device includes a first region and a second region, and the second region surrounds the first region. The semiconductor device includes at least one electronic unit, a redistribution structure, a plurality of first pads, and a plurality of second pads. The redistribution structure may be electrically connected to at least one electronic unit. A plurality of first pads are arranged on the redistribution structure and correspondingly to the first region. There is a first pitch between two adjacent first pads. A plurality of second pads are arranged on the redistribution structure and correspondingly to the second region. There is a second pitch between two adjacent second pads, so that the first pitch is smaller than the second pitch.Type: ApplicationFiled: December 18, 2022Publication date: May 2, 2024Applicant: InnoLux CorporationInventors: Te-Hsun LIN, Wen-Hsiang LIAO, Ming-Hsien SHIH, Yung-Feng CHEN, Cheng-Chi WANG
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Patent number: 11963295Abstract: Provided are a circuit apparatus, a manufacturing method thereof, and a circuit system. The circuit apparatus includes a flexible circuit board, a flexible packaging material layer and an electronic device. The flexible circuit board has at least one hollow pattern, wherein the flexible circuit board has an inner region and a peripheral region surrounding the inner region, and has a first surface and a second surface opposite to each other. The flexible packaging material layer is disposed in the at least one hollow pattern. The electronic device is disposed on the first surface of the flexible circuit board and electrically connected with the flexible circuit board.Type: GrantFiled: January 27, 2022Date of Patent: April 16, 2024Assignee: Industrial Technology Research InstituteInventors: Hung-Hsien Ko, Yi-Cheng Lu, Heng-Yin Chen, Hao-Wei Yu, Te-Hsun Lin
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Publication number: 20240120304Abstract: The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a package structure, a circuit structure, a bonding structure and an external element. The circuit structure is disposed on the package structure and is electrically connected to the package structure. The circuit structure has a recess. The bonding structure includes a first bonding pad and a second bonding pad. The second bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad. The bonding structure is disposed between the circuit structure and the external element. The external element is electrically connected to the circuit structure through the bonding structure. A width of the first bonding pad is smaller than a width of the second bonding pad.Type: ApplicationFiled: November 24, 2022Publication date: April 11, 2024Applicant: Innolux CorporationInventors: Tzu-Sheng Wu, Haw-Kuen Liu, Chung-Jyh Lin, Cheng-Chi Wang, Wen-Hsiang Liao, Te-Hsun Lin
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Publication number: 20230147556Abstract: A flexible hybrid electronic substrate and electronic textile including the same are provided. The flexible hybrid electronic substrate includes a first region and a second region. There is a joint between the first region and the second region. Each of the first region and the second region includes at least one selected from the group consisting of the following structure features: multilayer structure feature, anisotropic structure feature and pre-strained structure feature.Type: ApplicationFiled: January 27, 2022Publication date: May 11, 2023Applicant: Industrial Technology Research InstituteInventors: I-Hung Chiang, Hung-Hsien Ko, Min-Hsiung Liang, Te-Hsun Lin, Chen-Tsai Yang, Hao-Wei Yu
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Publication number: 20230138696Abstract: Provided are a circuit apparatus, a manufacturing method thereof, and a circuit system. The circuit apparatus includes a flexible circuit board, a flexible packaging material layer and an electronic device. The flexible circuit board has at least one hollow pattern, wherein the flexible circuit board has an inner region and a peripheral region surrounding the inner region, and has a first surface and a second surface opposite to each other. The flexible packaging material layer is disposed in the at least one hollow pattern. The electronic device is disposed on the first surface of the flexible circuit board and electrically connected with the flexible circuit board.Type: ApplicationFiled: January 27, 2022Publication date: May 4, 2023Applicant: Industrial Technology Research InstituteInventors: Hung-Hsien Ko, Yi-Cheng Lu, Heng-Yin Chen, Hao-Wei Yu, Te-Hsun Lin
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Publication number: 20220338309Abstract: A transparent film heater is provided, including a transparent conductive film, at least two main electrodes and at least four multiple electrodes. The transparent conductive film is disposed on a transparent substrate. At least two main electrodes are arranged on two sides of the transparent conductive film along an edge of the transparent conductive film. The at least four multiple electrodes are composed of a first pair of multiple electrodes and a second pair of multiple electrodes, and are arranged on the transparent conductive film. A first spacing region and a second spacing region are respectively located between adjacent end points of the two main electrodes along the edge of the transparent conductive film. The first pair of multiple electrodes are arranged in the first spacing region, and the second pair of multiple electrodes are arranged in the second spacing region.Type: ApplicationFiled: March 30, 2022Publication date: October 20, 2022Applicant: Industrial Technology Research InstituteInventors: Li-Wei Yao, Min-Hsiung Liang, Hsiao-Fen Wei, Yu-Pei Chang, Te-Hsun Lin, Chih-Chia Chang, Yen-Shu Lee
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Patent number: 11362045Abstract: A chip package structure including a substrate, a redistribution layer (RDL), a chip and an encapsulant is provided. The RDL is disposed on the substrate. The chip is disposed on the RDL and is electrically connected with the RDL. The encapsulant is disposed on the RDL and encapsulates the chip. The chip is located in the high stress region. From a top view, the chip is located in the high stress region, and the low stress region surrounds the high stress region. The RDL includes at least one first device located in the high stress region. From the top view, the extending direction of the at least one first device is parallel to a stress direction at a position thereof.Type: GrantFiled: February 18, 2020Date of Patent: June 14, 2022Assignee: Industrial Technology Research InstituteInventors: Te-Hsun Lin, Chen-Tsai Yang, Kuan-Chu Wu, Shao-An Yan
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Publication number: 20210183789Abstract: A chip package structure including a substrate, a redistribution layer (RDL), a chip and an encapsulant is provided. The RDL is disposed on the substrate. The chip is disposed on the RDL and is electrically connected with the RDL. The encapsulant is disposed on the RDL and encapsulates the chip. The chip is located in the high stress region. From a top view, the chip is located in the high stress region, and the low stress region surrounds the high stress region. The RDL includes at least one first device located in the high stress region. From the top view, the extending direction of the at least one first device is parallel to a stress direction at a position thereof.Type: ApplicationFiled: February 18, 2020Publication date: June 17, 2021Applicant: Industrial Technology Research InstituteInventors: Te-Hsun Lin, Chen-Tsai Yang, Kuan-Chu Wu, Shao-An Yan