Abstract: Test pad structures and methods of forming a test pad are described herein. A method for forming a test pad includes forming a device element over a substrate, depositing a dielectric layer over the device element and the substrate, and etching openings in the dielectric layer to a first depth. Once the openings have been formed, a conductive material is deposited in the openings and followed by a chemical mechanical planarization to form a first grid feature and a panel region of the test pad, the first grid feature extending lengthwise from the panel region to a perimeter of the test pad. Once formed, a probe may be used to contact the panel region of the test pad during a wafer acceptance test (WAT) and/or a process control monitoring (PCM) test of the device element.

Abstract: An adjustment circuit is included in a secondary-side controller, wherein the secondary-side controller is installed at a secondary side of an isolated power converter. The adjustment circuit includes a voltage divider, a buffer, a first variable resistor, a second variable resistor, an amplifier, and an N-type metal-oxide-semiconductor transistor. The buffer is coupled to the voltage divider. The first variable resistor is coupled to an external resistor outside the secondary-side controller. The second variable resistor is coupled to the first variable resistor and the buffer. The amplifier is coupled to the first variable resistor and the second variable resistor. The N-type metal-oxide-semiconductor transistor is coupled to a first external capacitor, a bias resistor, and an optocoupler. The first variable resistor and the second variable resistor adjust a characteristic of a Bode plot of the isolated power converter.

Abstract: A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.

Abstract: Test pad structures and methods of forming a test pad are described herein. A method for forming a test pad includes forming a device element over a substrate, depositing a dielectric layer over the device element and the substrate, and etching openings in the dielectric layer to a first depth. Once the openings have been formed, a conductive material is deposited in the openings and followed by a chemical mechanical planarization to form a first grid feature and a panel region of the test pad, the first grid feature extending lengthwise from the panel region to a perimeter of the test pad. Once formed, a probe may be used to contact the panel region of the test pad during a wafer acceptance test (WAT) and/or a process control monitoring (PCM) test of the device element.

Abstract: An optical fiber array includes a groove plate having a plurality of grooves disposed on a top surface thereof; and an optical component plate having a plurality of first optical components disposed on a first surface of the optical component plate and a plurality of second optical components disposed on a second surface of the optical component plate, the second surface being opposite the first surface.

Abstract: A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.

Abstract: A memory device and a control method of the memory device are provided. The memory device includes a memory array and a control logic circuit. The memory array includes a plurality of memory cell rows. The control logic circuit perform an access on the memory array. The control logic circuit counts a number of the access performed on the memory cell rows to generate a plurality of count values corresponding to the memory cell rows. When a count value corresponding to an accessed memory cell row among the memory cell rows is larger than or equal to a threshold value generated with random number corresponding to the accessed memory cell row, the control logic circuit arranges the memory cell rows nearby the accessed memory cell row into a mitigation operation.

Abstract: A pull cord release wheel for window blinds spring motor, and provides a release wheel for a spring motor of a curtain unit for winding a pull cord. The release wheel is mainly configured with a ridge at the corner joint position of a spoke, and pull cord access holes penetrate through a tread along with a planar ring spoke. Two through holes are formed on the tread enabling passage to the two side surfaces thereof, and an open space is provided at the outlet directions of the through holes. An outer circumference ridge surface of the ridge is used to take up a bunching force generated by a final winding of a second layer winding during the ascending process of a change in reverse winding of a third layer winding, thereby preventing squeezing a first winding that has been wound as an inner layer causing disordered winding.

Abstract: The present invention provides a cordless curtain and guide braking unit thereof, wherein the guide braking unit includes a fixing mount and a round rod shaped metal wire that is wound round to form a slide sheering member. The fixing mount is configured with a bottom block, and a pull cord through hole is provided in the center of the surface thereof. The slide sheering member is provided with a circular through-hole and fastening rod members, wherein the circular through-hole is axially positioned corresponding to the pull cord through hole, with the fastening rod members fixed to two sides of the circular through-hole. The inner circular edge of the circular through-hole is used to provide the pull cord with cornering slippage, which protects the various system components and produces the desired damping effect.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming an interconnect structure over a device wafer. The device wafer includes a first integrated circuit, a semiconductor substrate, and a redistribution structure. The method further includes forming a metallization layer and a group of dummy insertion structures having a stepped pattern density in a topmost dielectric layer of the interconnect structure. The group of dummy insertion structures and the metallization layer are planarized with the dielectric layer. The method further includes forming a first bonding layer over the group of dummy insertion structures, the metallization layer, and the dielectric layer. The method further includes bonding a carrier wafer to the first bonding layer, forming an opening through the semiconductor substrate, and forming a conductive via in the opening and electrically coupled to the redistribution structure.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming an interconnect structure over a device wafer. The device wafer includes a first integrated circuit, a semiconductor substrate, and a redistribution structure. The method further includes forming a metallization layer and a group of dummy insertion structures having a stepped pattern density in a topmost dielectric layer of the interconnect structure. The group of dummy insertion structures and the metallization layer are planarized with the dielectric layer. The method further includes forming a first bonding layer over the group of dummy insertion structures, the metallization layer, and the dielectric layer. The method further includes bonding a carrier wafer to the first bonding layer, forming an opening through the semiconductor substrate, and forming a conductive via in the opening and electrically coupled to the redistribution structure.

Abstract: The present invention relates to a composition comprising functionalized phosphonate, and water-soluble salt and N-oxide derivatives thereof, and method of use thereof as scale inhibitor. Particularly, the present invention relates to a composition comprising functionalized methylene phosphate of amino-terminated 52xyalkylated, a water-soluble salt thereof, a N-oxide salt thereof, or a water-soluble N-oxide salt thereof as scale inhibitor to prevent scales formed due to deposition of alkaline earth metal cations comprising (including) calcium, barium, strontium, magnesium, or a mixture thereof along with anions comprising (including) sulfate, carbonate, bicarbonate, phosphate, silicate, sulfide, or a mixture thereof, particularly to prevent scales formed due to deposition of calcium carbonate, calcium sulfate, barium sulfate, strontium sulfate, magnesium sulfate, or a mixture thereof at a different temperature and pressure in high salinity medium including brine environment.

Abstract: A composite barrier film, comprising: an ultra-thin barrier film, wherein the ultra-thin barrier film is capable of being water-resistant and oxygen-resistant; and a protection film, being attached on the ultra-thin barrier film for increasing the stiffness of the ultra-thin barrier film, wherein a thickness of the ultra-thin barrier film is less than a thickness of the protection film.

Abstract: A virtual reality acupuncture system contains a virtual reality device comprising: a head-mounted display for viewing a virtual scene model and a mannequin, and a joystick for tracking hand movements for needle insertion determination; an computing host that transmits data with a head-mounted display and constructs an acupoint database, and an acupuncture virtual reality application which is executed to build a virtual reality model, in which the acupuncture virtual reality application constructs a situational scene model for simulating the actual condition of the consultation room; and a virtual 3D spherical acupoint model of the human body, which has a sphere area located at a certain depth below the skin surface, and has a skin distance model, so that the needle can sense the distance depth after touching the skin, which can be used to determine whether the needle position is not outside the sphere area.

Abstract: A window blind position damping device is applied to a window blind with slat being expanded horizontally, forming a damping to a pull cord effectively when the slat is pulled down at any height, so as to define the height. The window blind position damping device includes a machine part, and an interior of the machine part has a spring scroll wheel and a position damping device which links a pull cord through a provided release idler. A damping shear pillar is vertically disposed on a base plate of the provided machine part, between an outlet of the release idler and an opening. By a provided shear ridge, the damping shear pillar shears an overrun section of the pull cord that passes through, forming the damping and thereby defining and fixing the slat at any height when being expanded.

Abstract: In an embodiment, a method includes performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure; performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition; planarizing the first bonding layer; forming a second bonding layer over a second substrate; pressing the second bonding layer onto the first bonding layer; and removing the first s

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: In an embodiment, a method includes performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure; performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition; planarizing the first bonding layer; forming a second bonding layer over a second substrate; pressing the second bonding layer onto the first bonding layer; and removing the first substrate.

Abstract: An ink circulation system, including an ink cartridge, an ink tank, an ink pump, first, second, and third valves, a print head, a heating assembly, and a positive-negative pressure assembly, is provided. The ink cartridge has an output pipeline and an ink cartridge valve. The ink tank is disposed on one side of the ink cartridge and connected to the output pipeline. The ink pump is connected to the output pipeline and the ink tank through an ink pipeline. The first valve is connected to the ink tank through a first pipeline. The second valve is disposed on the output pipeline. The third valve is connected to the output pipeline and the ink pipeline through a return pipeline. The print head is connected to the ink tank and the return pipeline. The heating assembly is disposed in the ink tank. The positive-negative pressure assembly is connected to the first pipeline.

Abstract: The present invention discloses a blind slat positioning device and a window blind thereof. The positioning device can fix the slat at any height at which the slat is pulled down. The positioning device includes a turning seat which is provided at least with an overbend element for a pull cord to wrap around. The overbend element includes at least a ridge, resulting an effect that the slat stops at the height at which the slat is pulled down, with the aid of gravity.