Abstract: A computer system architecture including a first buffer, a second buffer, a sub-system and a CPU is provided. The sub-system carries out a first task to obtain first returned information, stores the first returned information in the first buffer and sets up a first occupancy flag to the first buffer. Next, the sub-system carries out a second task to obtain second returned information, stores the second returned information in the second buffer, and sets up a second occupancy flag to the second buffer. The CPU reads the first returned information and eliminates the first occupancy flag. After the second returned information is stored in the second buffer and the first occupancy flag is eliminated, the sub-system continuously carries out a third task to obtain third returned information, stores the third returned information in the first buffer, and sets up the first occupancy flag to the first buffer.

Abstract: An adaptive memory address translation method includes the following steps. Multiple request instructions are received. A memory address corresponding to each request instruction includes a bank address. The memory addresses corresponding to the request instructions are translated, such that the bank addresses corresponding to at least one part of the any two adjacent request instructions are different. A numerical translation is utilized to translate the memory addresses corresponding to the request instructions, such that the memory addresses corresponding to the any two adjacent request instructions have less different bits.

Abstract: A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the one or more first request instructions and the one or more second request instructions to the memory. The control unit compares bandwidths of the one or more first request instructions with bandwidths of the one or more second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.

Abstract: A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the one or more first request instructions and the one or more second request instructions to the memory. The control unit compares bandwidths of the one or more first request instructions with bandwidths of the one or more second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.

Abstract: A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the first request instructions and the second request instructions to the memory. The control unit compares bandwidths of the first request instructions with bandwidths of the second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.

Abstract: A circuit system periodically checks a system-environment monitor value, and then obtains a system-environment monitor value index corresponding to the system-environment monitor value in the environment-adjustment look-up table. Finally, the circuit system adjusts a signal delay time according to a delay adjustment value corresponding to the system-environment monitor value index.

Abstract: An adaptive memory address translation method includes the following steps. Multiple request instructions are received. A memory address corresponding to each request instruction includes a bank address. The memory addresses corresponding to the request instructions are translated, such that the bank addresses corresponding to at least one part of the any two adjacent request instructions are different. A numerical translation is utilized to translate the memory addresses corresponding to the request instructions, such that the memory addresses corresponding to the any two adjacent request instructions have less different bits.

Abstract: A computer system architecture including a first buffer, a second buffer, a sub-system and a CPU is provided. The sub-system carries out a first task to obtain first returned information, stores the first returned information in the first buffer and sets up a first occupancy flag to the first buffer. Next, the sub-system carries out a second task to obtain second returned information, stores the second returned information in the second buffer, and sets up a second occupancy flag to the second buffer. The CPU reads the first returned information and eliminates the first occupancy flag. After the second returned information is stored in the second buffer and the first occupancy flag is eliminated, the sub-system continuously carries out a third task to obtain third returned information, stores the third returned information in the first buffer, and sets up the first occupancy flag to the first buffer.

Abstract: A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the first request instructions and the second request instructions to the memory. The control unit compares bandwidths of the first request instructions with bandwidths of the second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.

Abstract: A dynamic memory access method includes following steps. First, many data access commands are received. Each of the data access commands accesses a dynamic memory according to a page address and a bank address. Next, whether an access data to be accessed by the corresponding data access command is an instantaneous data or a non-instantaneous data is determined. Then, the page and bank addresses of each of the data access commands are respectively compared with a previously page and bank addresses at a previous time used for accessing the dynamic memory, such that an address hit status is obtained. Next, a service sequence is generated according to whether each of the data access commands is an instantaneous or instantaneous data and the address hit status of the commands. Finally, each of the data access commands is executed to access the dynamic memory sequentially according to the service sequence.

Abstract: A circuit system periodically checks a system-environment monitor value, and then obtains a system-environment monitor value index corresponding to the system-environment monitor value in the environment-adjustment look-up table. Finally, the circuit system adjusts a signal delay time according to a delay adjustment value corresponding to the system-environment monitor value index.

Abstract: A power-saving method of continuous display and effective cost in a system that includes memory directly accessed by a CPU and at least one display device within vertical blanking. The method includes the following steps: issuing a Power-saving related message; dropping the Power-saving related message, wherein a Power-saving related flag is not set; setting the Power-saving related flag; setting a VID/FID pending bit in the CPU, wherein the vertical blanking of the display/displays occurs and clearing the Power-saving related flag, wherein the Power-saving related flag is set, and executing a power saving process.

Abstract: A Power-saving method, which is able to configure not only the CPU but also the other computer devices, such as the host bus, GUI engine, South Bridge control engine . . . etc., into Power-saving state, has been proposed. The method includes the following steps: issuing a Power-saving related message; dropping the Power-saving related message, wherein a Power-saving related flag is not set; setting the Power-saving related flag; setting a VID/FID pending bit in the CPU, wherein the vertical blanking of the d display/displays occurs and clearing the Power-saving related flag, wherein the Power-saving related flag is set, and executing a power saving process. The Power-saving related flag may be built-in North Bridge, South Bridge or CPU.

Abstract: A method for preventing the long latency event in the working procedure of the processor is disclosed, wherein the method comprises one step of checking whether a status happens or not. When the status happens, the processor would release the resource for specific time duration to process other works in order to prevent the long latency event.

Abstract: A power-saving method of continuous display and effective cost in a system that includes memory directly accessed by a CPU and at least one display device within vertical blanking. The method includes the following steps: issuing a Power-saving related message; dropping the Power-saving related message, wherein a Power-saving related flag is not set; setting the Power-saving related flag; setting a VID/FID pending bit in the CPU, wherein the vertical blanking of the d display/displays occurs and clearing the Power-saving related flag, wherein the Power-saving related flag is set, and executing a power saving process.

Abstract: A memory address remapping method is disclosed. The memory address remapping method comprises: providing a cache-related address having a tag, an associative tag, a set index and a block offset; providing a linear operator; performing a linear calculation with a first linear operator input and a second linear operator input to obtain a first output, wherein the first linear operator input is several bits picked from the set index of the cache-related address according to a quantity and a corresponding location of a plurality of bits in the location address of a memory address, such as DDR memory-related address, Rambus memory-related address, etc.

Abstract: A memory read/write arbitration method is disclosed. The memory read/write arbitration method, which is utilized in a memory controller for increasing row hit rate and decreasing the delay of memory access, comprises: providing a arbitrator; providing a read request fifo queue having command read requests; providing a write request fifo queue having command write requests; performing a judgment step for generating a priority, wherein the judgment step comprises: performing a first sub-judgment step to determine that a command read request of the command read requests has priority over a command write request of the command write requests, or the command write request can be forwarded to a second sub-judgment step under adaptive first-step conditions; performing the second sub-judgment step to determine the read request has priority over the command write request from the first sub-judgment step, or the command write request from the first sub-judgment has priority over the command read request.