Abstract: An EEPROM segment bit line page memory array includes a plurality of bit lines extending in a Y-direction; a plurality of word lines extending in an X-direction; a plurality of sub-bit lines extending in the Y-direction; a plurality of segment select word lines extending in the X-direction; a plurality of segment select devices arranged in a segment select row; and a plurality of EEPROM floating gate memory devices arranged in the X- and Y-directions. Each of the segment select devices connects one of the sub-bit lines to a corresponding one of the bit-lines. Plural gates of the segment select devices in each segment select row are connected to one of the segment select word lines. Each of the memory devices connects adjacent sub-bit lines, and corresponding control gates of plural memory devices in a memory device row arc electrically connected to one of the word lines.

Abstract: A segmented bit-line EEPROM page architecture allows a reduction in memory cell size. An EEPROM segmented bit line page memory array comprises a plurality of bit lines extending in a Y column-direction; a plurality of word lines extending in an X row-direction; a plurality of sub-bit lines extending in the Y column-direction; a plurality of segment select word lines extending in the X-row direction; a plurality of segment select devices arranged in a segment select row; and a plurality of EEPROM floating gate memory devices arranged in the X-row and Y-column directions. Each of the segment select devices connects one of the sub-bit lines to a corresponding one of the bit-lines. Plural gates of the segment select devices in each segment select row are connected to one of the segment select word lines. Each of the memory devices connects adjacent sub-bit lines, and corresponding control gates of plural memory devices in a memory device row are electrically connected to one of the word lines.

Abstract: An EEPROM floating gate memory device includes: a floating gate disposed over the channel between the buried drain and the buried source, and insulated from the channel by 200 Å to 1000 Å of gate oxide; an add-on floating gate shorted electrically to the floating gate, and disposed over and insulated from the buried drain by 15 Å to 150 Å of tunnel dielectric; and a control gate disposed over and insulated from the floating gate and the channel between the floating gate and the buried source. Both the floating gate and the channel underneath are self-aligned to and flanked by the field oxide in the trench along the direction perpendicular to the channel current flow. The add-on floating gate forms both a self-aligned endcap on the field oxide and the self-aligned tunnel area on the buried drain. The architecture allows a reduction in memory cell size.

Abstract: A method of protecting a tunnel dielectric area from subsequent processing steps in EEPROM fabrication after formation of a memory cell poly 1 floating gate on a P-type substrate, including first implanting the substrate to form a buried N+ junction below and beside the floating gate, and then growing a first thin oxide layer over the N+ junction and on sidewalls of the floating gate and a selection device gate. A thin layer of polysilicon is deposited and then a second thin oxide layer is grown over the thin polysilicon layer. A photoresist is applied, and then removed from the top surface and the sidewalls of the gate structures. The second thin oxide layer is removed from the top surface and the vertical sidewalls of the gate structures.

Abstract: The present invention relates to a non-volatile dynamic random acess memory cell having a dynamic random access memory cell and an electrically-erasable and electrically-programmable memory device connected on the opposite sides of an insolation device. It also relates to a memory array of the non-volatile dynamic random access memory cells and the method of fabricating the same.

Abstract: The present invention relates to an air-water switching unit which consists of an air-water switching chamber with a movable piston residing inside the chamber and separating air coming into the chamber through an air inlet at one side and water coming into the chamber through a water inlet at the other side of the chamber. An air-water outlet is located between the air inlet and the water inlet. The movement of the piston is controlled by the pressure difference between the air pressure on one side and the water pressure on the other side of the piston. The air mixing water pump according to the present invention comprises the air-water switching unit, an air pump connected to the air inlet of the air-water switching chamber of the air-water switching unit, water supply from the output of a water filter connected to the water inlet of the air-water switching chamber, and a PVC tube connected to the air-water outlet of the air-water switching chamber.

Abstract: The EEPROM has the selection device in series with the memory device having a floating gate disposed over the channel between the buried drain and the buried source, and insulated from the channel by 200 A to 1000 A of gate oxide, an add-on floating gate shorted electrically to the floating gate, and disposed over and insulated from the buried drain by 40 A to 150 A of tunnel dielectric, and a control gate disposed over and insulated from the floating gate. The improvement in the proposed version of the memory device in the EEPROM is that the tunnel dielectric area is very small and is self aligned to the floating gate.

Abstract: The flash EEPROM memory device with the floating gate that is over the channel area and insulated from the channel by 200 to 1000 A of gate oxide, and that is also over the thin tunnel dielectric area at the source and insulated from the source by 70 A to 200 A of tunnel dielectric. Another improvement of the proposed version of the flash EEPROM memory device is that the tunnel dielectric area is small and self aligned to the floating gate.

Abstract: In this invention, an Electrically Alterable Non-Volatile Memory (EANOM) cell is disclosed. The EANOM ceil comprises an MOS transistor, having a source, a gate and a drain. The EANOM cell also has a two-terminal tunnel device, one end of which is connected to the gate of the MOS transistor. The other terminal being labelled "T". The tunnel device causes charges to be stored or removed from the gate of the MOS transistor. In a preferred embodiment, a four-terminal EANOM cell is disclosed. The four terminals of the EANOM cell are terminals T, S (source of the MOS transistor), D (drain of the MOS transistor) and a terminal C which is capacitively coupled to the gate of the MOS transistor. The EANOM cell can be used in a memory circuit to increase the reliability thereof. Two or more EANOM cells are connected in tandem and operate simultaneously. Catastrophic failure of one EANOM cell results in an open circuit with the other EANOM cell continuing to function.

Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.

Abstract: A method for fabricating an MOS memory array is disclosed, wherein the method includes steps for constructing electrically-programmable and electrically-erasable memory cells (2, 198, 200) in combination with assorted peripheral devices (202, 204, 206) on a semiconductor substrate (8, 71). Tunneling regions (20, 78) are formed in the substrate (8, 71) and thin tunnel dielectrics (22, 84) comprised of silicon dioxide/oxynitride material are grown over the tunneling regions (20, 78) to facilitate transport of charge carriers between the tunneling regions (20, 78) and subsequently-fashioned floating gate structures (14R, 14L, 156) in the memory cells (2, 198, 200). A first layer of doped polycrystalline silicon is then deposited over the substrate and etched to define large polysilicon areas. An oxide layer is grown over the large polysilicon areas in a manner such that out-diffusion of the impurity present in the large polysilicon areas is prevented.

Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.

Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.

Abstract: Integrated circuit resistor elements ideally suited for load devices in static MOS RAM cells are made in second-level polycrystalline silicon by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The second-level polysilicon is insulated from first-level polysilicon by multi-layer insulation; first, a thermal oxide layer provides better edge breakdown characteristics for transistors, then secondly a layer of doped deposited oxide provides improved step coverage, and finally an undoped deposited oxide is used to prevent out diffusion from doped oxide to second level polysilicon which would change the characteristics of the resistors.

Abstract: The chime unit of pre-programmed melody type and that of programmable melody type for the electric clock and the mechanical clock. The chime units consist of the hour and the minute hands position sensing means using magnetic Reed switches or photo-transistors, melody decoding circuits using D-type Flip Flop to trigger counters to provide proper addressing signals to ROMs or RAMs, ROMs or RAMs which contain pre-programmed control signals of multiplexers, notes synthesizer generating all tones needed as input to multiplexers, multiplexers for selecting and mixing the tones from notes synthesizer to form the chime notes, decay generator and voltage controlled amplifier to provide decaying characteristics of chime notes, and speaker to convert electrical signal to mechanical sound. For the programmable melody type, there is an additional notes decoder to convert the notes to the control signals of the multiplexers and store in RAMs.

Abstract: A non-volatile semiconductor memory device of the electrically erasable type employs a floating gate which is programmed by application to high voltage across the source and drain so that hot electrons traverse the gate oxide. The floating gate is discharged by electron tunneling through an erase window which is separated from the control gate. Very small cell size is provided by a triple level polysilicon structure.

Abstract: Integrated circuit resistor elements ideally suited for load devices in static MOS RAM cells are made in second-level polycrystalline silicon by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The second-level polysilicon is insulated from first-level polysilicon by multi-layer insulation; first, a thermal oxide layer provides better edge breakdown characteristics for transistors, then secondly a layer of doped deposited oxide provides improved step coverage, and finally an undoped deposited oxide is used to prevent out diffusion from doped oxide to second level polysilicon which would change the characteristics of the resistors.

Abstract: in a field effect transistor having a semiconductor body, spaced source and drain regions, an insulating layer on the surface of the body, and an electrode to the source region, the improvement being a field shield electrode on the insulating layer overlying at least the PN junction of the drain region that terminates at the interface of the surface of the body and the insulating layer, and a gate electrode on the insulating layer over at least a portion of the channel region, the gate electrode and the field shield electrode in combination overlying all of the channel region. Another feature of the invention is a high voltage line for use on a semiconductor device consisting of a diffused region of opposite conductivity in the semiconductor body, an overlying insulating layer having an opening therein, and an overlying field shield conductive stripe that overlies the PN junction of the diffused region that terminates at the surface of the body.