Patents by Inventor TE-MING KUNG

TE-MING KUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200341926
    Abstract: An electronic apparatus installed with non-volatile memory express solid state disks (NVMe SSDs) is provided. The electronic apparatus includes a processor, a board management controller (BMC), a micro-controller, at least one first input and output (IO) expander, and a plurality of NVMe SSDs. The micro-controller is coupled to the processor and the BMC. The first IO expander is coupled between the micro-controller and the NVMe SSDs. The micro-controller reads a PRSNT # information and an IFDET # information of each of the NVMe SSDs through the first IO expander, and transmits the PRSNT # information and the IFDET # information of each of the NVMe SSDs to the processor and the BMC.
    Type: Application
    Filed: October 4, 2019
    Publication date: October 29, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chang-Yu Tu, Te-Ming Kung, Wen-Shyan Lai
  • Publication number: 20200098591
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Application
    Filed: May 1, 2019
    Publication date: March 26, 2020
    Inventors: Yi-Sheng Lin, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, Te-Ming Kung, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Chun-Wei Hsu, Yang-Chun Cheng
  • Publication number: 20180156552
    Abstract: A thermal simulation system adapted to establish a test environment for a thermal test is provided. The thermal simulation system includes a communication element, a controllable loading element, a plurality of connectors, and a controller. The communication element is configured to receive at least one of a heating control signal, a fan control signal, and a loading control signal from an external electronic device. The controllable loading element is configured to provide a loading. The connectors are configured to connect a heating element and a fan. The controller is configured to control a heat energy generated by the heating element according to the heating control signal, control a fan speed of the fan according to the fan control signal, and control a loading value of the loading provided by the controllable loading element according to the loading control signal.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 7, 2018
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chang-Yu Tu, Te-Ming Kung, Wen-Shyan Lai, Tung-Hua Wu
  • Publication number: 20170168964
    Abstract: A hard drive disk indicator processing apparatus includes first and second processors. The first processor includes first, second and third communication interfaces. The first communication interface receives at least one serial general purpose input/output signal from a motherboard. The second communication interface receives a plurality piece of hard drive disk status information for responding to a plurality of hard drive disk statuses of hard drive disks. The third communication interface outputs serial information. The second processor includes fourth and fifth communication interfaces. The fourth communication interface is coupled to the third communication interface and receives the serial information. The fifth communication interface is coupled to a plurality of hard drive disk indicators. The first processor generates the serial information according to the at least one serial general purpose input/output signal.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 15, 2017
    Inventors: Te-Ming Kung, Chang-Yu Tu, Wen-Shyan Lai
  • Patent number: 9502647
    Abstract: A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a resistance-switching network disposed between the pair of electrodes. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer. The group-IV doping layer comprises silicon oxide doped with a group-IV element. The porous low-k layer comprises porous silicon oxide or porous hafnium oxide. The group-IV element may comprise zirconium, titanium, or hafnium. The porous low-k layer may be prepared by inductively coupled plasma (ICP) treatment. A method of fabricating a resistive memory is disclosed. The method comprises forming a resistance-switching network on a first electrode using sputtering and forming a second electrode on the resistance-switching network using sputtering. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Chih-Hung Pan, Ying-Lang Wang, Kei-Wei Chen, Shih-Chieh Chang, Te-Ming Kung
  • Patent number: 9368394
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a semiconductor substrate; forming a conductive region at least partially in the semiconductor substrate; forming a dielectric layer over the substrate; forming a hard mask over the dielectric layer, the hard mask having an opening over the conductive region; dry etching the dielectric layer by a first etching gas to form a recessed feature, wherein a surface of the conductive region is therefore exposed at a bottom of the recessed feature, and a byproduct film is formed at an inner surface of the recessed feature; and dry etching the dielectric layer by a second etching gas, wherein the second etching gas chemically reacts with the byproduct film and the conductive region, and a sacrificial layer is therefore built up around the bottom of the recessed feature.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: June 14, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Li Hung, Te-Ming Kung, Chih-Hao Chen, Kei-Wei Chen, Ying-Lang Wang, Hung Jui Chang, Horng-Huei Tseng
  • Patent number: 9281475
    Abstract: A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a multi-layer resistance-switching network disposed between the pair of electrodes. The multi-layer resistance-switching network comprises a pair of carbon doping layers and a group-IV element doping layer disposed between the pair of carbon doping layers. Each carbon doping layer comprises silicon oxide doped with carbon. The group-IV doping layer comprises silicon oxide doped with a group-IV element. A method of fabricating a resistive memory cell is also disclosed. The method comprises forming a first carbon doping layer on a first electrode using sputtering, forming a group-IV element doping layer on the first carbon doping layer using sputtering, forming a second carbon doping layer on the group-IV element doping layer using sputtering, and forming a second electrode on the second carbon doping layer using sputtering.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Chih-Hung Pan, Ying-Lang Wang, Kei-Wei Chen, Shih-Chieh Chang, Te-Ming Kung
  • Publication number: 20150349250
    Abstract: A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a multi-layer resistance-switching network disposed between the pair of electrodes. The multi-layer resistance-switching network comprises a pair of carbon doping layers and a group-IV element doping layer disposed between the pair of carbon doping layers. Each carbon doping layer comprises silicon oxide doped with carbon. The group-IV doping layer comprises silicon oxide doped with a group-IV element. A method of fabricating a resistive memory cell is also disclosed. The method comprises forming a first carbon doping layer on a first electrode using sputtering, forming a group-IV element doping layer on the first carbon doping layer using sputtering, forming a second carbon doping layer on the group-IV element doping layer using sputtering, and forming a second electrode on the second carbon doping layer using sputtering.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: TING-CHANG CHANG, KUAN-CHANG CHANG, TSUNG-MING TSAI, CHIH-HUNG PAN, YING-LANG WANG, KEI-WEI CHEN, SHIH-CHIEH CHANG, TE-MING KUNG
  • Publication number: 20150349251
    Abstract: A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a resistance-switching network disposed between the pair of electrodes. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer. The group-IV doping layer comprises silicon oxide doped with a group-IV element. The porous low-k layer comprises porous silicon oxide or porous hafnium oxide. The group-IV element may comprise zirconium, titanium, or hafnium. The porous low-k layer may be prepared by inductively coupled plasma (ICP) treatment. A method of fabricating a resistive memory is disclosed. The method comprises forming a resistance-switching network on a first electrode using sputtering and forming a second electrode on the resistance-switching network using sputtering. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: TING-CHANG CHANG, KUAN-CHANG CHANG, TSUNG-MING TSAI, CHIH-HUNG PAN, YING-LANG WANG, KEI-WEI CHEN, SHIH-CHIEH CHANG, TE-MING KUNG