Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Abstract: A testing circuit for testing a universal serial bus (USB) of an electronic device includes a controller, a first switch, a pull-down resistor, a gating pull-up resistor, and a second switch. The controller provides a control signal according to a power receiving condition of the electronic device. A control terminal of the first switch is coupled to the controller. The pull-down resistor is coupled between a configuration channel pin of the USB and a first terminal of the first switch. The gating pull-up resistor is coupled between the configuration channel pin and the control terminal of the first switch. A control terminal of the second switch is coupled to the controller. A first terminal of the second switch is coupled to a second terminal of the first switch and a ground pin of the USB. A second terminal of the second switch is coupled to a reference low voltage.

Abstract: A method of evaluating a thickness of a film on a substrate includes detecting atomic force responses of the film to exposure of electromagnetic radiation in the infrared portion of the electromagnetic spectrum. The use of atomic force microscopy to evaluate thicknesses of thin films avoids underlayer noise commonly encountered when optical metrology techniques are utilized to evaluate film thicknesses. Such underlayer noise adversely impacts the accuracy of the thickness evaluation.

Abstract: A testing system and a testing method are provided. The testing system includes a first testing device and a second testing device. The first testing device is coupled to a first stream facing-port of a device under test (DUT). The first testing device includes a controller. The second testing device is coupled to a second stream facing-port of the DUT. The controller transmits a testing signal to the DUT through the first stream facing-port to test a universal serial bus (USB) of the DUT. The DUT is operated based on the testing signal to generate a data signal. The DUT outputs the data signal to the second testing device through the second stream facing-port. The second testing device obtains status information of the DUT which is operated based on the testing signal 10 to generate a testing result. The controller determines whether the DUT is normal according to the testing result.

Abstract: A semiconductor structure includes a substrate, a nanowire disposed over the substrate, a metal gate electrode layer and a gate dielectric layer. A dielectric layer is formed on the substrate. The nanowire has a first portion and a second portion. The nanowire has a first portion and a second portion, the first portion of the nanowire comprises a first semiconductor layer and a second semiconductor layer surrounded by the first semiconductor layer, the second portion comprises the second semiconductor layer. The metal gate electrode layer surrounds the first portion of the nanowire. The gate dielectric layer is disposed between the metal gate electrode layer and the nanowire.

Abstract: A testing circuit for testing a universal serial bus (USB) of an electronic device includes a controller, a first switch, a pull-down resistor, a gating pull-up resistor, and a second switch. The controller provides a control signal according to a power receiving condition of the electronic device. A control terminal of the first switch is coupled to the controller. The pull-down resistor is coupled between a configuration channel pin of the USB and a first terminal of the first switch. The gating pull-up resistor is coupled between the configuration channel pin and the control terminal of the first switch. A control terminal of the second switch is coupled to the controller. A first terminal of the second switch is coupled to a second terminal of the first switch and a ground pin of the USB. A second terminal of the second switch is coupled to a reference low voltage.

Abstract: A method of forming a semiconductor structure includes following operations. A substrate including a silicon (Si) layer is received. An amorphous germanium (Ge) layer is formed on the Si layer. A barrier layer is formed over the amorphous Ge layer. The substrate is annealed to transform the Si layer and the Ge layer to form a single crystalline SiGe layer. A Ge concentration is in a positive correlation with a ratio of a thickness of the Ge layer and a thickness of the Si layer.

Abstract: A method of evaluating a thickness of a film on a substrate includes detecting atomic force responses of the film to exposure of electromagnetic radiation in the infrared portion of the electromagnetic spectrum. The use of atomic force microscopy to evaluate thicknesses of thin films avoids underlayer noise commonly encountered when optical metrology techniques are utilized to evaluate film thicknesses. Such underlayer noise adversely impacts the accuracy of the thickness evaluation.

Abstract: A method of evaluating a thickness of a film on a substrate includes detecting atomic force responses of the film to exposure of electromagnetic radiation in the infrared portion of the electromagnetic spectrum. The use of atomic force microscopy to evaluate thicknesses of thin films avoids underlayer noise commonly encountered when optical metrology techniques are utilized to evaluate film thicknesses. Such underlayer noise adversely impacts the accuracy of the thickness evaluation.

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Abstract: A method of forming a semiconductor structure includes following operations. A substrate including a silicon (Si) layer is received. An amorphous germanium (Ge) layer is formed on the Si layer. A barrier layer is formed over the amorphous Ge layer. The substrate is annealed to transform the Si layer and the Ge layer to form a single crystalline SiGe layer. A Ge concentration is in a positive correlation with a ratio of a thickness of the Ge layer and a thickness of the Si layer.

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Abstract: A method of evaluating a thickness of a film on a substrate includes detecting atomic force responses of the film to exposure of electromagnetic radiation in the infrared portion of the electromagnetic spectrum. The use of atomic force microscopy to evaluate thicknesses of thin films avoids underlayer noise commonly encountered when optical metrology techniques are utilized to evaluate film thicknesses. Such underlayer noise adversely impacts the accuracy of the thickness evaluation.

Abstract: A method of evaluating a thickness of a film on a substrate includes detecting atomic force responses of the film to exposure of electromagnetic radiation in the infrared portion of the electromagnetic spectrum. The use of atomic force microscopy to evaluate thicknesses of thin films avoids underlayer noise commonly encountered when optical metrology techniques are utilized to evaluate film thicknesses. Such underlayer noise adversely impacts the accuracy of the thickness evaluation.

Abstract: A method of evaluating a thickness of a film on a substrate includes detecting atomic force responses of the film to exposure of electromagnetic radiation in the infrared portion of the electromagnetic spectrum. The use of atomic force microscopy to evaluate thicknesses of thin films avoids underlayer noise commonly encountered when optical metrology techniques are utilized to evaluate film thicknesses. Such underlayer noise adversely impacts the accuracy of the thickness evaluation.

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Abstract: An electronic apparatus installed with non-volatile memory express solid state disks (NVMe SSDs) is provided. The electronic apparatus includes a processor, a board management controller (BMC), a micro-controller, at least one first input and output (IO) expander, and a plurality of NVMe SSDs. The micro-controller is coupled to the processor and the BMC. The first IO expander is coupled between the micro-controller and the NVMe SSDs. The micro-controller reads a PRSNT # information and an IFDET # information of each of the NVMe SSDs through the first IO expander, and transmits the PRSNT # information and the IFDET # information of each of the NVMe SSDs to the processor and the BMC.

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Abstract: A thermal simulation system adapted to establish a test environment for a thermal test is provided. The thermal simulation system includes a communication element, a controllable loading element, a plurality of connectors, and a controller. The communication element is configured to receive at least one of a heating control signal, a fan control signal, and a loading control signal from an external electronic device. The controllable loading element is configured to provide a loading. The connectors are configured to connect a heating element and a fan. The controller is configured to control a heat energy generated by the heating element according to the heating control signal, control a fan speed of the fan according to the fan control signal, and control a loading value of the loading provided by the controllable loading element according to the loading control signal.