Patents by Inventor Te O Jung

Te O Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8854400
    Abstract: Provided are a method and system for controlling light by using an image code. The method includes displaying an image code on a display unit; acquiring information relating to light settings by recognizing the image code; determining apparatus information and lighting state information by using information relating to the light settings; and transmitting a light request message for requesting light settings according to the lighting state information to the lighting apparatus having apparatus information that is equal to the apparatus information of the image code.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-gon Lee, Te-o Jung, Chang-sub Lee, Sang-hun Lee
  • Publication number: 20120274670
    Abstract: Provided are a method and system for controlling light by using an image code. The method includes displaying an image code on a display unit; acquiring information relating to light settings by recognizing the image code; determining apparatus information and lighting state information by using information relating to the light settings; and transmitting a light request message for requesting light settings according to the lighting state information to the lighting apparatus having apparatus information that is equal to the apparatus information of the image code.
    Type: Application
    Filed: April 27, 2012
    Publication date: November 1, 2012
    Inventors: Sang-gon LEE, Te-o JUNG, Chang-sub LEE, Sang-hun LEE
  • Publication number: 20120212140
    Abstract: A lighting controlling apparatus including: a management server generating control information based on information received from a user; a digital addressable lighting interface (DALI) master that is connected to the management server via wired or wireless communication and generates a control message based on the control information; and a DALI ballast that is connected to the DALI master via DALI communication and drives a lighting apparatus by using the control message. Accordingly, a plurality of DALI masters may be locally or remotely controlled via the management server. Also, not only the DALI ballast may be controlled by using the DALI master via DALI communication but also, it may be selectively controlled in regard to the relationship between a DALI switch. In addition, the DALI ballast may be directly controlled by using a sensor and a remote controller.
    Type: Application
    Filed: January 19, 2012
    Publication date: August 23, 2012
    Inventors: Ki-young KIM, Sang-hun Lee, Nam-yeol Lee, Sang-gon Lee, Te-o Jung, Chang-sub Lee
  • Publication number: 20120153862
    Abstract: Provided is an apparatus that drives a light emitting device using an erasable programmable logic device (EPLD) chip. The apparatus may include the light emitting device, and a driving unit to use the EPLD chip storing programming information corresponding to the light emitting device, and to drive the light emitting device based on the stored programming information. The EPLD chip may receive the programming information inputted from an external terminal, and may store the programming information in a predetermined storage space.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 21, 2012
    Inventors: Sang Hun Lee, Chang Sub Lee, Ki Young Kim, Min Su Kim, Sang Gon Lee, Te O Jung, Jin Ho Park
  • Patent number: 7303963
    Abstract: Disclosed herein is a method of manufacturing a cell transistor which can achieve an improvement in a short-channel effect of a cell transistor as well as an improvement in a refresh characteristic of the transistor, and can also prevent a reduction in the threshold voltage of the transistor, in relation to DRAM memory cells with high integration. The method comprises the steps of forming a device isolation region, which defines a device separating region, on a silicon substrate, forming a barrier layer on the substrate formed with device isolation region, forming a hard mask, which defines a gate forming region, on the substrate formed with the barrier layer, forming a silicon epitaxial layer on a surface of the substrate through selective epitaxial growth of silicon constituting the surface of the substrate, formed with the hard mask and the barrier layer, and removing the hard mask.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: December 4, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Te O Jung
  • Publication number: 20050277261
    Abstract: Disclosed herein is a method of manufacturing a cell transistor which can achieve an improvement in a short-channel effect of a cell transistor as well as an improvement in a refresh characteristic of the transistor, and can also prevent a reduction in the threshold voltage of the transistor, in relation to DRAM memory cells with high integration. The method comprises the steps of forming a device isolation region, which defines a device separating region, on a silicon substrate, forming a barrier layer on the substrate formed with device isolation region, forming a hard mask, which defines a gate forming region, on the substrate formed with the barrier layer, forming a silicon epitaxial layer on a surface of the substrate through selective epitaxial growth of silicon constituting the surface of the substrate, formed with the hard mask and the barrier layer, and removing the hard mask.
    Type: Application
    Filed: January 18, 2005
    Publication date: December 15, 2005
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Te O Jung