Abstract: A computing system for accessing a dynamic random access memory (DRAM) includes a processing circuit, a queue, and a DRAM controller. The processing circuit is configured for issuing an early notification signal before issuing a clock frequency switch signal; the early notification signal notifies of an approaching clock frequency switch signal and the clock frequency switch signal requests a change of frequency of a DRAM clock. The queue stores commands to be sent to the DRAM for a plurality of operations to access the DRAM. The DRAM controller is configured for controlling access to the DRAM and the DRAM controller manages to reschedule the commands of the queue to issue ongoing commands for currently processed operation, issue a command for modifying the setting of the DRAM and pause the issuance of remaining unfinished commands of remaining unfinished operations to the DRAM upon receiving the early notification signal.

Abstract: A computing system for accessing a dynamic random access memory (DRAM) includes a processing circuit, a queue, and a DRAM controller. The processing circuit is configured for issuing an early notification signal before issuing a clock frequency switch signal; the early notification signal notifies upcoming of the clock frequency switch signal and the clock frequency switch signal requests a change of frequency of a DRAM clock. The queue has N entries and each entry stores at least an address and an associated command to be sent to the DRAM. The DRAM controller is configured for controlling access to the DRAM and the DRAM controller manages to decrease occupancy of the queue to a target level upon receiving the early notification signal.

Abstract: A computing system for accessing a dynamic random access memory (DRAM) includes a processing circuit, a queue, and a DRAM controller. The processing circuit is configured for issuing an early notification signal before issuing a clock frequency switch signal; the early notification signal notifies upcoming of the clock frequency switch signal and the clock frequency switch signal requests a change of frequency of a DRAM clock. The queue has N entries and each entry stores at least an address and an associated command to be sent to the DRAM. The DRAM controller is configured for controlling access to the DRAM and the DRAM controller manages to decrease occupancy of the queue to a target level upon receiving the early notification signal.