Patents by Inventor Te-Sun Wu
Te-Sun Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110089888Abstract: A notebook computer battery pack device charges an external electrical device and powers a notebook computer. The notebook computer battery pack device includes battery cells for converting chemical energy into direct current power, a first interface connector for transferring the direct current power to a notebook computer, a second interface connector for transferring the direct current power to the external electrical device, battery management circuitry for providing circuit protection, and charging circuitry for charging the external electrical device through the second interface connector.Type: ApplicationFiled: January 4, 2010Publication date: April 21, 2011Inventors: Tung-Cheng Kuo, Chun-Ming Chen, Huei-Chia Lo, Te-Sun Wu
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Patent number: 7205614Abstract: A high density read-only memory (ROM) cell is installed on a silicon substrate for storing data. The ROM cell includes a first doped region being of a second conductive type installed on the silicon substrate, a plurality of first heavily doped regions being of a first conductive type installed in the first doped region, a second doped region being of the second conductive type installed on the silicon substrate, and a gate installed on the surface of the silicon substrate and adjacent to the first doped region and the second doped region.Type: GrantFiled: January 6, 2004Date of Patent: April 17, 2007Assignee: Faraday Technology Corp.Inventors: Sheng-Tai Young, Te-Sun Wu, Tsung-Yuan Lee, Chih-Kang Chiu
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Patent number: 7079433Abstract: A wafer level burn-in method for static-random access memory. The SRAM memory has a plurality of word lines and a plurality of bit lines. The SRAM memory also has pull up circuits and equalizer circuits connected to various bit lines. All the word lines are switched on for testing any leakage in the gate dielectric layer. A high potential is applied to a bit line of every bit line pairs and a low potential is applied to the other bit line of the bit line pairs. The pull-up circuits and the equalizer circuits are shut down. The current at a steady state is used to judge the normality of an SRAM chip.Type: GrantFiled: May 18, 2001Date of Patent: July 18, 2006Assignee: United Microelectronics Corp.Inventors: Chih-Hung Chen, Te-Sun Wu
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Publication number: 20050207568Abstract: A communicating apparatus generating low echo includes an output module, a receiving module and a control unit. The output module directs a remote voice signal outputted from the control unit, so that the remote signal is transmitted along a specific direction within a specific range. The receiving module receives a local signal, and transmits to the control unit thereby. Wherein the remote audio signal transmitted from the output module is excluded from the receiving module, thus echo is lowered significantly and communication quality is enhanced.Type: ApplicationFiled: April 12, 2004Publication date: September 22, 2005Inventor: Te-Sun Wu
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Publication number: 20050145948Abstract: A high density read-only memory (ROM) cell is installed on a silicon substrate for storing data. The ROM cell includes a first doped region being of a second conductive type installed on the silicon substrate, a plurality of first heavily doped regions being of a first conductive type installed in the first doped region, a second doped region being of the second conductive type installed on the silicon substrate, and a gate installed on the surface of the silicon substrate and adjacent to the first doped region and the second doped region.Type: ApplicationFiled: January 6, 2004Publication date: July 7, 2005Inventors: Sheng-Tai Young, Te-Sun Wu, Tsung-Yuan Lee, Chih-Kang Chiu
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Patent number: 6420859Abstract: A voltage supply control apparatus, suitable for being applied to a low voltage operation device. The voltage supply control apparatus has a high threshold voltage transistor and a low threshold voltage transistor. When the low voltage operation device is not working, the low threshold voltage transistor is cut off, and the voltage drop of a high voltage received from the power source terminal of the low voltage operation device is controlled by the high threshold voltage transistor. In contrast, when the low voltage operation device is working, the operation enable signal output thereby conducts the low threshold voltage transistor to control the voltage drop of the high voltage received from the power source terminal, so that a high potential is obtained.Type: GrantFiled: February 27, 2001Date of Patent: July 16, 2002Assignee: United Microelectronics Corp.Inventors: Hui Fang Tsai, Chin Shin Yeh, Te Sun Wu
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Patent number: 6014018Abstract: A voltage-reducing device of low power dissipation is provided, including a plurality of transistors, which are self-connected as diode equivalent. These transistors are then cascaded in series in the same direction and coupled to a voltage source. Since every transistor has a threshold voltage, the voltage at the end of the forward-biased cascaded transistors will be lowered than the voltage source so as to provide a reduced voltage source. Furthermore, since the voltage adjustment of the device is based on the threshold voltage, there is hardly any power dissipation. In addition, we can use different threshold voltages from various transistors to provide different combinations of these threshold voltages to obtain the desired voltage drop.Type: GrantFiled: October 22, 1998Date of Patent: January 11, 2000Assignee: United Microelectronics Corp.Inventors: Te-Sun Wu, Hui-Fang Tsai, Tsun-Zu Lin
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Patent number: 5939900Abstract: An input buffer which is coupled to a direct voltage source and ground, includes at least one CMOS device and an enhancement mode NMOS transistor, receives at least one input signal and provides one output signal. The input buffer makes use of the enhancement mode NMOS transistor to lower the potential difference between the gate terminal and the source terminal of the PMOS transistor of the CMOS device. Thus, the input buffer can lower the turning on degree of the PMOS transistor effectively. Then the PMOS transistor which is considered as a pull-up transistor can lower the degree to which the input buffer is turned on, and maintain the characteristics and functionality of the input buffer.Type: GrantFiled: December 31, 1996Date of Patent: August 17, 1999Assignee: United Microelectronics Corp.Inventor: Te Sun Wu
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Patent number: 5620915Abstract: The ROM device comprises a number of memory cells each is constructed based on a MOS transistor, the memory cells in the ROM are arranged into a number of rows and a columns. A number of word lines each connects to the gates of each of the MOS transistors of all the memory cells in each of the rows. A number of bit lines each connects to one of the source/drain pair of each of the MOS transistors of all the memory cells in each of the columns. A multiplexer comprises a number of transmitting transistors, each of the transmitting transistors is connected to a corresponding one of the bit lines, forming a current flow path including the transmitting transistor, the connected bit line, and the memory cells correspondingly connected to the bit line. A sense amplifier is coupled to the multiplexer for sensing the current flowing therethrough the current flow path to output a corresponding sense output signal.Type: GrantFiled: July 12, 1995Date of Patent: April 15, 1997Assignee: United Microelectronics CorporationInventors: Hsin-Li Chen, Te-Sun Wu
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Patent number: 5572056Abstract: A ROM is formed by depositing a first layer composed of a material selected from polysilicon and polycide on the substrate, patterning the first layer by masking and etching, depositing a dielectric layer over the first layer and patterning the dielectric layer and the first layer into the pattern of first conductor lines, forming a contact window through the dielectric layer down to the substrate, depositing a second layer composed of a material selected from polysilicon and polycide on the device and forming second conductor lines directed orthogonally to the first conductor lines formed from the first layer, and ion implanting into the substrate through the second layer to form a contact region electrically connected to the second conductor lines of the second layer.Type: GrantFiled: December 29, 1994Date of Patent: November 5, 1996Assignee: United Microelectronics CorporationInventors: Chen-Chiu Hsue, Ming-Tzong Yang, Te-Sun Wu
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Patent number: 5572147Abstract: A voltage detector for determining the high or low status of a power supply output voltage, including a front-end detector and an inverting amplifier. The front-end detector includes a number of NMOS and PMOS transistors which constitute active loads. The voltage detector is inherently independent of device fabrication condition changes, as well as on the temperature variations.Type: GrantFiled: September 8, 1995Date of Patent: November 5, 1996Assignee: United Microelectronics CorporationInventors: Heng-Sheng Huang, Kun-Lun Chen, Te-Sun Wu
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Patent number: 5561624Abstract: A ROM array with coding after metallization comprises a plurality of first bit lines, a plurality of second bit lines, a plurality of third bit lines, a plurality of word lines, a plurality of first control lines, a plurality of second control lines and a plurality of selecting lines. Memory cells of the ROM array are formed by the intersection of the word lines and the first and second bit lines, wherein the word lines are polysilicon gates and the bit lines are drain/source diffusion regions. The third bit lines are metal lines above the first bit lines. The third bit lines are not wide enough to cover spacings between the first and second bit lines, thus exposing spaces for code implantation. The first and second control lines intersect the first and second bit lines to form a number of switches for controlling data reading paths to The memory cells. The positions and ON/OFF states of the switches are designed to provide at least two data reading paths to each memory cell.Type: GrantFiled: June 26, 1995Date of Patent: October 1, 1996Assignee: United Microelectronics Corp.Inventors: Hsin-Li Chen, Te-Sun Wu, Kai-Chi Hsieh
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Patent number: 5493527Abstract: A read only memory cell array and method of operation thereof comprises an array of memory transistor cells, a plurality of word lines, a plurality of bit lines, a plurality of select bit lines, a plurality of bank select lines for enabling reading of a selected bank in the array connected to bank select transistors in the bank, a select even line adapted for enabling reading of even cells in a selected bank connected to select even cell transistors in the bank, and a select odd line adapted for enabling reading of odd cells in a selected bank connected to select odd cell transistors in the array.Type: GrantFiled: January 9, 1995Date of Patent: February 20, 1996Assignee: United Micro Electronics CorporationInventors: Han-Shen Lo, Te-Sun Wu, Stephen S. Fu
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Patent number: 5475637Abstract: A mask ROM device having active bit-line clamp circuits which employ a voltage-to-current converter as the clamp circuit for selectively coupling a main bit line of the ROM memory device to a selected one of virtual ground lines. The voltage-to-current converter is selectively coupled between the main bit line and a first or second virtual ground line for clamping therebetween. The voltage-to-current converter converts the voltage difference between the coupled main bit line and the selected first or second virtual ground line into a corresponding current in proportion to a voltage difference, the converted current being coupled to the selected first or second virtual ground line.Type: GrantFiled: December 27, 1994Date of Patent: December 12, 1995Assignee: United Microelectronics Corp.Inventors: Stephen Fu, Te-Sun Wu
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Patent number: 5380676Abstract: A ROM is formed by depositing a first layer composed of a material selected from polysilicon and polycide on the substrate, patterning the first layer by masking and etching, depositing a dielectric layer over the first layer and patterning the dielectric layer and the first layer into the pattern of first conductor lines, forming a contact window through the dielectric layer down to the substrate, depositing a second layer composed of a material selected from polysilicon and polycide on the device and forming second conductor lines directed orthogonally to the first conductor lines formed from the first layer, and ion implanting into the substrate through the second layer to form a contact region electrically connected to the second conductor lines of the second layer.Type: GrantFiled: May 23, 1994Date of Patent: January 10, 1995Assignee: United Microelectronics CorporationInventors: Chen-Chiu Hsue, Ming-Tzong Yang, Te-Sun Wu
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Patent number: 5330924Abstract: A cost-effective and manufacturable method for producing ROM integrated circuits with closely-spaced self-aligned conductive lines, on the order of 0.3 micrometers apart, is described. Parallel, conductive semiconductor device structures are formed in a semiconductor substrate. An insulating layer is formed over the semiconductor substrate. A first conductive polysilicon layer is formed over the insulating layer. The first conductive polysilicon layer is patterned to form first polysilicon conductor lines which are parallel to each other, and orthogonal to the parallel, conductive semiconductor device structures. A first silicon oxide layer is formed on and between the first polysilicon conductor lines. The first silicon oxide layer is anisotropically etched to produce sidewall structures on the first polysilicon conductor lines. A second silicon oxide layer is formed on and between the first polysilicon conductor lines.Type: GrantFiled: November 19, 1993Date of Patent: July 19, 1994Assignee: United Microelectronics CorporationInventors: Heng S. Huang, Kun-Luh Chen, Te-Sun Wu, Han-Shen Lo