Patents by Inventor Te-Sung Wu
Te-Sung Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130299868Abstract: Methods of forming devices, including LED devices, are described. The devices may include fluorinated compound layers. The methods described may utilize a plasma treatment to form the fluorinated compound layers. The methods described may operate to produce an intermetallic layer that bonds two substrates such as semiconductor wafers together in a relatively efficient and inexpensive manner.Type: ApplicationFiled: July 17, 2013Publication date: November 14, 2013Inventors: Owen Fay, Xiao Li, Josh Woodland, Shijian Luo, Jaspreet Gandhi, Te-Sung Wu
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Patent number: 8492242Abstract: Methods of forming devices, including LED devices, are described. The devices may include fluorinated compound layers. The methods described may utilize a plasma treatment to form the fluorinated compound layers. The methods described may operate to produce an intermetallic layer that bonds two substrates such as semiconductor wafers together in a relatively efficient and inexpensive manner.Type: GrantFiled: May 25, 2010Date of Patent: July 23, 2013Assignee: Micron Technology, Inc.Inventors: Owen Fay, Xiao Li, Josh Woodland, Shijian Luo, Jaspreet Gandhi, Te-Sung Wu
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Publication number: 20110291146Abstract: Methods of forming devices, including LED devices, are described. The devices may include fluorinated compound layers. The methods described may utilize a plasma treatment to form the fluorinated compound layers. The methods described may operate to produce an intermetallic layer that bonds two substrates such as semiconductor wafers together in a relatively efficient and inexpensive manner.Type: ApplicationFiled: May 25, 2010Publication date: December 1, 2011Applicant: Micron Technology, Inc.Inventors: Owen Fay, Xiao Li, Josh Woodland, Shijian Luo, Jaspreet Gandhi, Te-Sung Wu
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Patent number: 6784089Abstract: A method of making an electrical contact bump electrical contact structure on a substrate comprising: providing a substrate having a bond pad, and a passivation layer overlying a portion for the substrate and wherein the passivation layer includes an opening therein exposing a portion of the bond pad, and wherein the passivation layer has a raised portion overlying the bond pad; forming an under bump metallurgy over at least the exposed portion of the bond pad and over at least a portion of the raised portion of the passivation layer overlying the bond pad; forming a sacrificial blanket having an opening therein that in cross-section has an inverted T-shape over the substrate so that the opening in the sacrificial blanket is aligned with the bond pad; and depositing an electrically conductive material into the opening in the sacrificial blanket.Type: GrantFiled: January 13, 2003Date of Patent: August 31, 2004Assignee: Aptos CorporationInventors: Kuolung Lei, Tony Shen, Susana Samoranos, Te-Sung Wu, Tsing-Chow Wang
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Publication number: 20040137707Abstract: A method of making an electrical contact bump electrical contact structure on a substrate comprising: providing a substrate having a bond pad, and a passivation layer overlying a portion of the substrate and wherein the passivation layer includes an opening therein exposing a portion of the bond pad, and wherein the passivation layer has a raised portion overlying the bond pad; forming an under bump metallurgy over at least the exposed portion of the bond pad and over at least a portion of the raised portion of the passivation layer overlying the bond pad; forming a sacrificial blanket having an opening therein that in cross-section has an inverted T-shape over the substrate so that the opening in the sacrificial blanket is aligned with the bond pad; and depositing an electrically conductive material into the opening in the sacrificial blanket.Type: ApplicationFiled: January 13, 2003Publication date: July 15, 2004Applicant: Aptos CorporationInventors: Kuolung Lei, Tony Shen, Susana Samoranos, Te-Sung Wu, Tsing-Chow Wang
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Patent number: 6524645Abstract: A process for the metalization of substrates is disclosed. The metal either forms a coating over the entire substrate, or it is patternwise deposited on the substrate surface. Metal is patternwise formed on the substrate either by forming a pattern of resist material on the substrate and depositing the material in the interstices defined by the pattern or by forming a patterned resist layer over a metal layer and transferring the pattern into the substrate using conventional techniques. The patterned resist layer is formed on the substrate using conventional techniques. The substrate is treated with reagents that promote the electroless plating of metal on the substrate surface. If the resist material has been previously formed on the substrate surface, the substrate surface is then dried. The remaining resist is then removed from the substrate surface.Type: GrantFiled: October 18, 1994Date of Patent: February 25, 2003Assignee: Agere Systems Inc.Inventors: Michael D. Evans, Tae Yong Kim, Henry Hon Law, Te-Sung Wu
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Patent number: 6448171Abstract: Within a method for fabricating a microelectronic fabrication, and a microelectronic fabrication fabricated employing the method, there is first provided a substrate. Within the method, there is then formed over the substrate a patterned bond pad layer. There is also formed over the substrate a patterned passivation layer which passivates a series of edges of the patterned bond pad layer while leaving exposed a central portion of the patterned bond pad layer, where the patterned passivation layer has a series of protrusions within the patterned passivation layer over the series of edges of the patterned bond pad layer. There is then formed over the central portion of the patterned bond pad layer and bridging over the series of protrusions of the patterned passivation layer a first terminal electrode layer having an upper surface which is concave. Finally, there is then formed over the first terminal electrode layer a second terminal electrode layer having an upper surface which is other than concave.Type: GrantFiled: May 5, 2000Date of Patent: September 10, 2002Assignee: Aptos CorporationInventors: Tsing-Chow Wang, Te-Sung Wu
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Patent number: 6362087Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a patterned bond pad layer. There is also formed over the substrate and in electrical communication with the patterned bond pad layer a patterned redistribution layer, wherein the patterned redistribution layer is formed employing a plating method. The method is particularly economical for fabricating the microelectronic fabrication.Type: GrantFiled: May 5, 2000Date of Patent: March 26, 2002Assignee: Aptos CorporationInventors: Tsing-Chow Wang, Te-Sung Wu, Erh-Kong Chieh
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Patent number: 5779873Abstract: This invention is predicated on the discovery by the present applicants that boric acid in conventional nickel plating baths is responsible for excessive lateral growth in the electroplating of nickel on nickel ferrite substrates. While nickel baths without boric acid do not yield acceptable electrodeposits, the boric acid interacts with the ferrite substrate to cause excessive lateral growth. Applicants further discovered that by eliminating the boric acid and adding another acidic plating buffer such as citric acid, one can obtain isotropic nickel plating and produce a wire-bondable surface.Type: GrantFiled: December 18, 1996Date of Patent: July 14, 1998Assignee: Lucent Technologies Inc.Inventors: Henry Hon Law, Lynn Frances Schneemeyer, Te-Sung Wu
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Patent number: 5619791Abstract: The thickness uniformity of a plated metal layer inside a via hole can be enhanced by intersecting a conductive via with an insulating aperture before plating. The new via configuration improves the mass transfer of the plating. It is believed that the apertures lower the local solution ohmic resistance near the via holes. The method can be applied to the manufacture of a wide variety of circuit boards.Type: GrantFiled: April 28, 1995Date of Patent: April 15, 1997Assignee: Lucent Technologies Inc.Inventors: Vincent G. Lambrecht, Jr., Henry H. Law, Apurba Roy, John Thomson, Jr., Te-Sung Wu
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Patent number: 5618611Abstract: The present invention provides a method for metallizing a ceramic surface comprising a ferrite through a surface reduction treatment. A ceramic surface comprising a ferrite is heated. At least a portion of the ferrite is contacted with a gaseous reducing agent to create a metallic region by removing oxygen from the ferrite. The surface is cooled and, optionally, post-treated to enhance adhesion of the metallic region. Typical gaseous reducing agents are hydrogen, forming gas, and ammonia while typical ferrites are nickel-zinc ferrites and manganese-zinc ferrites. To form patterned regions, portions of the substrate are masked or portions of the reduced layer are removed.Type: GrantFiled: April 25, 1995Date of Patent: April 8, 1997Assignee: Lucent Technologies Inc.Inventors: Sungho Jin, Henry H. Law, Thomas H. Tiefel, Te-Sung Wu