Patents by Inventor Te-Yi Yu

Te-Yi Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of detecting connection defects of memory and memory capable of detecting connection defects thereof
    Patent number: 8773931
    Abstract: By inputting voltages to global word lines of a memory, and by detecting currents of corresponding global word lines, a relation function between the currents and the voltages can be generated, and connection defects on the global word lines can be determined according to various types of deviation of a relation curve corresponding to the relation function between the currents and voltages.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 8, 2014
    Assignee: Etron Technology, Inc.
    Inventors: Min-Chih Chang, Shih-Hsing Wang, Te-Yi Yu, Lien-Sheng Yang
  • Method of Detecting Connection Defects of Memory and Memory Capable of Detecting Connection Defects thereof
    Publication number: 20130010558
    Abstract: By inputting voltages to global word lines of a memory, and by detecting currents of corresponding global word lines, a relation function between the currents and the voltages can be generated, and connection defects on the global word lines can be determined according to various types of deviation of a relation curve corresponding to the relation function between the currents and voltages.
    Type: Application
    Filed: June 18, 2012
    Publication date: January 10, 2013
    Inventors: Min-Chih Chang, Shih-Hsing Wang, Te-Yi Yu, Lien-Sheng Yang
  • Memory device capable of operation in a burn in stress mode, method for performing burn in stress on a memory device, and method for detecting leakage current of a memory device
    Patent number: 8331178
    Abstract: Activate one active word line of two active word lines formed between two isolation word lines to a logic-high voltage, and float another active word line of the two active word lines. Then activate a plurality of first memory cells corresponding to the active word line having the logic-high voltage to a logic “1” voltage, and write a logic “0” voltage to a plurality of second memory cells corresponding to the floating active word line. Then write the logic “1” voltage to a plurality of bit lines. Then, suspend for charge sharing for a third predetermined time. Finally, read a voltage of the floating active word line to check if any leakage path exists between the floating active word line and the active word line having the logic-high voltage.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: December 11, 2012
    Assignee: Etron Technology, Inc.
    Inventors: Shi-Huei Liu, Tzu-Hao Chen, Te-Yi Yu, Ming-Hong Kuo
  • MEMORY DEVICE CAPABLE OF OPERATION IN A BURN IN STRESS MODE, METHOD FOR PERFORMING BURN IN STRESS ON A MEMORY DEVICE, AND METHOD FOR DETECTING LEAKAGE CURRENT OF A MEMORY DEVICE
    Publication number: 20120163107
    Abstract: Activate one active word line of two active word lines formed between two isolation word lines to a logic-high voltage, and float another active word line of the two active word lines. Then activate a plurality of first memory cells corresponding to the active word line having the logic-high voltage to a logic “1” voltage, and write a logic “0” voltage to a plurality of second memory cells corresponding to the floating active word line. Then write the logic “1” voltage to a plurality of bit lines. Then, suspend for charge sharing for a third predetermined time. Finally, read a voltage of the floating active word line to check if any leakage path exists between the floating active word line and the active word line having the logic-high voltage.
    Type: Application
    Filed: November 23, 2011
    Publication date: June 28, 2012
    Inventors: Shi-Huei Liu, Tzu-Hao Chen, Te-Yi Yu, Ming-Hong Kuo