Abstract: The present disclosure provides a dual-lens movement control method, which includes steps as follows. The tracking target is detected through the wide-angle lens, and the final tracking range is calculated; the magnification and the position are determined according to the final tracking range; the separate mode or the alignment mode is determined according to the magnification and the position.

Abstract: A virtual assistant negotiation method is provided, which includes the following steps: transmitting an event information by a first electronic device corresponding to an initiator; receiving a plurality of candidate projects generated by second electronic devices corresponding to a plurality of participants according to the event information by the first electronic devices; selecting a portion of the candidate projects to serve as recommended projects by the first electronic device of the host; and making a decision according to the opinions, for the recommended projects, corresponding to the main participant among the participants by the first electronic device.

Abstract: The present disclosure provides a dual-lens movement control method, which includes steps as follows. The tracking target is detected through the wide-angle lens, and the final tracking range is calculated; the magnification and the position are determined according to the final tracking range; the separate mode or the alignment mode is determined according to the magnification and the position.

Abstract: A virtual assistant negotiation method is provided, which includes the following steps: transmitting an event information by a first electronic device corresponding to an initiator; receiving a plurality of candidate projects generated by second electronic devices corresponding to a plurality of participants according to the event information by the first electronic devices; selecting a portion of the candidate projects to serve as recommended projects by the first electronic device of the host; and making a decision according to the opinions, for the recommended projects, corresponding to the main participant among the participants by the first electronic device.

Abstract: A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

Abstract: A layout of an integrated circuit design is provided and a plurality of multiple patterning decompositions is determined from the layout. Each decomposition of the plurality of multiple patterning decompositions includes patterns separated into masks. One or more files are generated that include sensitivities of pattern capacitances to changes in spacing between patterns due to mask shifts. Using the sensitivities and changes in spacing, respective worst-case performance values are determined for each decomposition. A mask set is selected based on the worst-case performance values.

Abstract: A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

Abstract: A method of designing a circuit layout includes calculating a typical value representing performance characteristics for the circuit layout based on a graphic database system (GDS) file. The method further includes calculating an adjustment value based on the GDS file and at least one of a CAP corner vector or a RES corner vector, wherein the CAP corner vector is based on an eigenvector of a parasitic capacitance of the circuit layout, and the RES corner vector is based on an eigenvector of a parasitic resistance of the circuit layout. The method further includes calculating a corner value based on the typical value and the adjustment value. The method further includes modifying the GDS file if performance characteristics of the corner value fail to satisfy performance requirements of the circuit layout.

Abstract: A layout of an integrated circuit design is provided and a plurality of multiple patterning decompositions is determined from the layout. Each decomposition of the plurality of multiple patterning decompositions includes patterns separated into masks. One or more files are generated that include sensitivities of pattern capacitances to changes in spacing between patterns due to mask shifts. Using the sensitivities and changes in spacing, respective worst-case performance values are determined for each decomposition. A mask set is selected based on the worst-case performance values.

Abstract: A system and method comprising providing a layout of an integrated circuit design, generating, by a processor, a plurality of multiple patterning decompositions from the layout, determining a maximum mask shift between the first mask and the second mask and simulating a worst-case performance value for each of the plurality of multiple patterning decompositions using one or more mask shifts within a range defined by the maximum mask shift. Further, each of the plurality of multiple patterning decompositions comprise patterns separated to a first mask and a second mask of a multiple patterning mask set.

Abstract: A method of designing a circuit layout includes calculating a typical value representing performance characteristics for the circuit layout based on a graphic database system (GDS) file. The method further includes calculating an adjustment value based on the GDS file and at least one of a CAP corner vector or a RES corner vector, wherein the CAP corner vector is based on an eigenvector of a parasitic capacitance of the circuit layout, and the RES corner vector is based on an eigenvector of a parasitic resistance of the circuit layout. The method further includes calculating a corner value based on the typical value and the adjustment value. The method further includes modifying the GDS file if performance characteristics of the corner value fail to satisfy performance requirements of the circuit layout.

Abstract: A system and method comprising providing a layout of an integrated circuit design, generating, by a processor, a plurality of multiple patterning decompositions from the layout, determining a maximum mask shift between the first mask and the second mask and simulating a worst-case performance value for each of the plurality of multiple patterning decompositions using one or more mask shifts within a range defined by the maximum mask shift. Further, each of the plurality of multiple patterning decompositions comprise patterns separated to a first mask and a second mask of a multiple patterning mask set.

Abstract: The method for extracting a capacitance from a layout is disclosed. The method decomposes a first net into a first and a second component, and decomposes a second net into a third and a fourth component. The method may obtain a first capacitance for the first component and the third component by a first method, and obtain a second capacitance for the second component and the fourth component by a second method different from the first method. A library with a plurality of entries may be provided, wherein each entry has a component pair comprising a component of the first net and a component of the second net, and a pre-calculated capacitance for the component pair. The first method may be to search a library to find a pre-calculated capacitance. The second method may be to obtain the first capacitance by an equation solver on the fly.

Abstract: Among other things, one or more systems and techniques for width bias adjustment for a design layout are provided. During fabrication, characteristics of a component can change, such as size, width, position, etc., from how a design layout represents such components. Accordingly, a width bias table is used to identify a width bias value that can be applied between a first polygon and a second polygon to compensate for a characteristic change associated with at least one of the first polygon and the second polygon during fabrication. The width bias value is used during RC extraction to determine an electrical characteristic adjustment, such as an additional capacitance or resistance associated with the width bias value, for at least one of the first polygon and the second polygon. In this way, RC extraction, during a design phase, can take into account electrical characteristic changes that occur during fabrication.

Abstract: The present disclosure relates to a method of RC extraction that provides for a fast development time and easy maintenance. In some embodiments, the method provides a graphical representation of an integrated chip layout having a plurality of integrated chip components. A plurality of pattern based graphical features are then determined. Respective pattern based graphical features define a structural aspect of an integrated chip component. One of the plurality of integrated chip components is defined as a pattern oriented function having inputs of one or more of the pattern based graphical features. The pattern oriented function determines a shape of the one of the plurality of integrated chip components based upon a relation between the plurality of inputs. By determining a shape of an integrated chip component using a pattern oriented function, the complexity of RC profiles can be reduced.

Abstract: The method for extracting a capacitance from a layout is disclosed. The method decomposes a first net into a first and a second component, and decomposes a second net into a third and a fourth component. The method may obtain a first capacitance for the first component and the third component by a first method, and obtain a second capacitance for the second component and the fourth component by a second method different from the first method. A library with a plurality of entries may be provided, wherein each entry has a component pair comprising a component of the first net and a component of the second net, and a pre-calculated capacitance for the component pair. The first method may be to search a library to find a pre-calculated capacitance. The second method may be to obtain the first capacitance by an equation solver on the fly.

Abstract: The present disclosure relates to a method of RC extraction that provides for a fast development time and easy maintenance. In some embodiments, the method provides a graphical representation of an integrated chip layout having a plurality of integrated chip components. A plurality of pattern based graphical features are then determined. Respective pattern based graphical features define a structural aspect of an integrated chip component. One of the plurality of integrated chip components is defined as a pattern oriented function having inputs of one or more of the pattern based graphical features. The pattern oriented function determines a shape of the one of the plurality of integrated chip components based upon a relation between the plurality of inputs. By determining a shape of an integrated chip component using a pattern oriented function, the complexity of RC profiles can be reduced.

Abstract: The method for extracting a capacitance from a layout is disclosed. The method decomposes a first net into a first and a second component, and decomposes a second net into a third and a fourth component. The method may obtain a first capacitance for the first component and the third component by a first method, and obtain a second capacitance for the second component and the fourth component by a second method different from the first method. A library with a plurality of entries may be provided, wherein each entry has a component pair comprising a component of the first net and a component of the second net, and a pre-calculated capacitance for the component pair. The first method may be to search a library to find a pre-calculated capacitance. The second method may be to obtain the first capacitance by an equation solver on the fly.