Abstract: A semiconductor package includes a sequential stack of first and second semiconductor chips, and a first internal connection member that connects the first and second semiconductor chips to each other. The first semiconductor chip includes a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and a first conductive pad on the first top surface. The second semiconductor chip includes a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and a second conductive bump on the second bottom surface. The first internal connection member connects the first conductive pad to the second conductive bump. The first conductive pad has a first width in one direction. The second conductive bump has a second width in the one direction. The first width is smaller than the second width.

Abstract: A semiconductor package includes a sequential stack of first and second semiconductor chips, and a first internal connection member that connects the first and second semiconductor chips to each other. The first semiconductor chip includes a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and a first conductive pad on the first top surface. The second semiconductor chip includes a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and a second conductive bump on the second bottom surface. The first internal connection member connects the first conductive pad to the second conductive bump. The first conductive pad has a first width in one direction. The second conductive bump has a second width in the one direction. The first width is smaller than the second width.

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

Abstract: Disclosed is a semiconductor package with increased thermal radiation efficiency, which includes: a first die having signal and dummy regions and including first vias in the signal region, a second die on the first die and including second vias in the signal region, first die pads on a top surface of the first die and coupled to the first vias, first connection terminals on the first die pads which couple the second vias to the first vias, second die pads in the dummy region and on the top surface of the first die, and second connection terminals on the second die pads and electrically insulated from the first vias and the second vias. Each of the second die pads has a rectangular planar shape whose major axis is provided along a direction that leads away from the signal region.

Abstract: There is provided a semiconductor device comprising a first semiconductor chip which includes a first chip substrate, and a first through via penetrating the first chip substrate, a second semiconductor chip disposed on the first semiconductor chip, and includes a second chip substrate, and a second through via penetrating the second chip substrate, and a connecting terminal disposed between the first semiconductor chip and the second semiconductor chip to electrically connect the first through via and the second through via. The semiconductor device further comprising an inter-chip molding material which includes a filling portion that fills between the first semiconductor chip and the second semiconductor chip and encloses the connecting terminal, an extension portion that extends along at least a part of a side surface of the second semiconductor chip, and a protruding portion protruding from the extension portion.

Abstract: A semiconductor package includes a sequential stack of first and second semiconductor chips, and a first internal connection member that connects the first and second semiconductor chips to each other. The first semiconductor chip includes a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and a first conductive pad on the first top surface. The second semiconductor chip includes a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and a second conductive bump on the second bottom surface. The first internal connection member connects the first conductive pad to the second conductive bump. The first conductive pad has a first width in one direction. The second conductive bump has a second width in the one direction. The first width is smaller than the second width.

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

Abstract: A semiconductor package includes a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a second through substrate via connected to the first through substrate via. A side surface of the first adhesive layer is recessed from side surfaces of the first and second semiconductor chips.

Abstract: A method of cutting a substrate including a device region and a scribe lane region includes selectively forming a passivation layer in the device region of the substrate, selectively forming a self-assembled monolayer on the passivation layer, and performing plasma cutting in the scribe lane region.

Abstract: A semiconductor package includes a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a second through substrate via connected to the first through substrate via. A side surface of the first adhesive layer is recessed from side surfaces of the first and second semiconductor chips.

Abstract: A method of cutting a substrate including a device region and a scribe lane region includes selectively forming a passivation layer in the device region of the substrate, selectively forming a self-assembled monolayer on the passivation layer, and performing plasma cutting in the scribe lane region.

Abstract: A semiconductor package includes a first semiconductor chip stacked on a package substrate in which a first surface of the first semiconductor chip faces the package substrate and a second surface that is opposite to the first surface, a second semiconductor chip stacked on the first semiconductor chip that includes a third surface facing the first semiconductor chip and a fourth surface that is opposite to the third surface, and an integral adhesive structure that substantially continuously fills a first space between the package substrate and the first semiconductor chip and a second space between the first and second semiconductor chips. The integral adhesive structure includes an extension protruding from outer sidewalls of the first and second semiconductor chips. The extension has one continuously convex sidewall between a level of the first surface and a level of the fourth surface.

Abstract: A semiconductor package includes a first semiconductor chip stacked on a package substrate in which a first surface of the first semiconductor chip faces the package substrate and a second surface that is opposite to the first surface, a second semiconductor chip stacked on the first semiconductor chip that includes a third surface facing the first semiconductor chip and a fourth surface that is opposite to the third surface, and an integral adhesive structure that substantially continuously fills a first space between the package substrate and the first semiconductor chip and a second space between the first and second semiconductor chips. The integral adhesive structure includes an extension protruding from outer sidewalls of the first and second semiconductor chips. The extension has one continuously convex sidewall between a level of the first surface and a level of the fourth surface.

Abstract: A semiconductor package includes a first semiconductor chip on a substrate and having a plurality of through-silicon vias (TSVs). A second semiconductor chip having an active layer is on the first semiconductor chip. An adhesive layer is between the first semiconductor chip and the active layer. Connection terminals extend through the adhesive layer and are connected to the TSVs and the active layer. Side surfaces of the adhesive layer are aligned with side surfaces of the second semiconductor chip.

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract: A substrate of a semiconductor package includes a first wiring substrate having a first surface and a second surface facing each other, the first surface having a semiconductor chip mounted thereon, a first support carrier, and an adhesive film connecting the second surface and the first support carrier.